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fsp_baytrail: Update microcode for Gold 3 FSP release 

New microcode for Bay Trail I B2/B3 and D0 parts was released in the
Gold 3 Bay Trail FSP release.

Change the microcode size to an area instead of the exact size of the
patches.  This will hopefully reduce updates to the microcode size.

Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7647
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Martin Roth 2014-12-04 18:12:20 -07:00 committed by Martin Roth
parent e10108a669
commit bb27316264
2 changed files with 9 additions and 3 deletions
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10
src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
View File

@ -19,8 +19,14 @@
unsigned microcode[] = { unsigned microcode[] = {
/* Size is 0x19800 - update in microcode_size.h when a patch gets changed. */ /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
#include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 #include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1
#include "M013067331E.h" // M0130673: Baytrail I B2 / B3 #include "M0130673322.h" // M0130673: Baytrail I B2 / B3
#include "M0130679901.h" // M0130679: Baytrail I D0
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
}; };

2
src/soc/intel/fsp_baytrail/microcode/microcode_size.h
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@ -1,2 +1,2 @@
/* Maximum size of the area that the FSP will search for the correct microcode */ /* Maximum size of the area that the FSP will search for the correct microcode */
#define MICROCODE_REGION_LENGTH 0x19800 #define MICROCODE_REGION_LENGTH 0x30000