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mb/google/sarien: Disable pcie interface for wwan 

WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the
usgae of Sarien choose to only use USB interface but not over pci
express, so totally disable pci express root port 12.

BUG=b:1246720
TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10
cyles can still device can be listed under lsusb.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d
Reviewed-on: https://review.coreboot.org/c/30350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Lijian Zhao 2018-12-20 21:34:40 -08:00 committed by Duncan Laurie
parent 7ec8d4b8f0
commit bb3d01a249
2 changed files with 2 additions and 12 deletions
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7
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -86,11 +86,6 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[1]" = "10"
register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 12 for M.2 3042
register "PcieRpEnable[11]" = "1"
register "PcieClkSrcUsage[3]" = "11"
register "PcieClkSrcClkReq[3]" = "3"
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "1"
register "PcieClkSrcUsage[4]" = "12"
@ -240,7 +235,7 @@ chip soc/intel/cannonlake
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10
device pci 1d.2 on end # PCI Express Port 11
device pci 1d.3 on end # PCI Express Port 12
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1

7
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -95,11 +95,6 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[1]" = "9"
register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 12 for M.2 3042
register "PcieRpEnable[11]" = "1"
register "PcieClkSrcUsage[0]" = "11"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "1"
register "PcieClkSrcUsage[2]" = "12"
@ -259,7 +254,7 @@ chip soc/intel/cannonlake
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 on end # PCI Express Port 12
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1