soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macro

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d098a55a5c6f6e022c3896750c752e2759e101b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/cezanne/i2c.c

@@ -37,13 +37,11 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
 	const struct soc_amd_cezanne_config *config = config_of_soc();
 	uint32_t pad_ctrl;
-	int misc_reg;
 
 	if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel))
 		return;
 
-	misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus;
+	pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
-	pad_ctrl = misc_read32(misc_reg);
 
 	pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
 	pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
@@ -55,7 +53,7 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 	pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
 		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
 	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
-	misc_write32(misc_reg, pad_ctrl);
+	misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
 }
 
 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)

src/soc/amd/cezanne/include/soc/southbridge.h

@@ -116,6 +116,7 @@
 #define MISC_I2C1_PAD_CTRL		0xdc
 #define MISC_I2C2_PAD_CTRL		0xe0
 #define MISC_I2C3_PAD_CTRL		0xe4
+#define MISC_I2C_PAD_CTRL(bus)		(MISC_I2C0_PAD_CTRL + 4 * (bus))
 #define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
 #define     I2C_PAD_CTRL_NG_NORMAL	0xc
 #define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))

src/soc/amd/picasso/i2c.c

@@ -41,10 +41,8 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
 	uint32_t pad_ctrl;
-	int misc_reg;
 
-	misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus;
+	pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
-	pad_ctrl = misc_read32(misc_reg);
 
 	pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
 	pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
@@ -57,7 +55,7 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
 	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
 
-	misc_write32(misc_reg, pad_ctrl);
+	misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
 }
 
 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)

src/soc/amd/picasso/include/soc/southbridge.h

@@ -96,6 +96,7 @@
 #define MISC_I2C1_PAD_CTRL		0xdc
 #define MISC_I2C2_PAD_CTRL		0xe0
 #define MISC_I2C3_PAD_CTRL		0xe4
+#define MISC_I2C_PAD_CTRL(bus)		(MISC_I2C0_PAD_CTRL + 4 * (bus))
 #define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
 #define     I2C_PAD_CTRL_NG_NORMAL	0xc
 #define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))

src/soc/amd/sabrina/i2c.c

@@ -39,13 +39,11 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
 	const struct soc_amd_sabrina_config *config = config_of_soc();
 	uint32_t pad_ctrl;
-	int misc_reg;
 
 	if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel))
 		return;
 
-	misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus;
+	pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
-	pad_ctrl = misc_read32(misc_reg);
 
 	pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
 	pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
@@ -57,7 +55,7 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 	pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
 		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
 	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
-	misc_write32(misc_reg, pad_ctrl);
+	misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
 }
 
 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)

src/soc/amd/sabrina/include/soc/southbridge.h

@@ -117,6 +117,7 @@
 #define MISC_I2C1_PAD_CTRL		0xdc
 #define MISC_I2C2_PAD_CTRL		0xe0
 #define MISC_I2C3_PAD_CTRL		0xe4
+#define MISC_I2C_PAD_CTRL(bus)		(MISC_I2C0_PAD_CTRL + 4 * (bus))
 #define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
 #define     I2C_PAD_CTRL_NG_NORMAL	0xc
 #define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))