diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 87fec55ef6..2ead963f12 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -94,7 +94,7 @@ static void sio_init(void)
 {
 	u8 reg;
 
-	pnp_enter_ext_func_mode(SERIAL_DEV);
+	pnp_enter_conf_state(SERIAL_DEV);
 	/* We have 24MHz input. */
 	reg = pnp_read_config(SERIAL_DEV, 0x24);
 	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
@@ -104,9 +104,9 @@ static void sio_init(void)
 	/* We have all RESTOUT and even some reserved bits, too. */
 	reg = pnp_read_config(SERIAL_DEV, 0x2c);
 	pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
-	pnp_exit_ext_func_mode(SERIAL_DEV);
+	pnp_exit_conf_state(SERIAL_DEV);
 
-	pnp_enter_ext_func_mode(ACPI_DEV);
+	pnp_enter_conf_state(ACPI_DEV);
 	pnp_set_logical_device(ACPI_DEV);
 	/*
 	 * Set the delay rising time from PWROK_LP to PWROK_ST to
@@ -117,9 +117,9 @@ static void sio_init(void)
 	/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
 	reg = pnp_read_config(ACPI_DEV, 0xe4);
 	pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
-	pnp_exit_ext_func_mode(ACPI_DEV);
+	pnp_exit_conf_state(ACPI_DEV);
 
-	pnp_enter_ext_func_mode(GPIO_DEV);
+	pnp_enter_conf_state(GPIO_DEV);
 	pnp_set_logical_device(GPIO_DEV);
 	/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
 	pnp_write_config(GPIO_DEV, 0x30, 0x09);	/* Enable GPIO 2 & GPIO 5. */
@@ -129,7 +129,7 @@ static void sio_init(void)
 	pnp_write_config(GPIO_DEV, 0xe0, 0xde);	/* 1101 1110, 0 = output 1 = input */
 	pnp_write_config(GPIO_DEV, 0xe1, 0x01);	/* Set output val. */
 	pnp_write_config(GPIO_DEV, 0xe4, 0xb4);	/* Set output val (1011 0100). */
-	pnp_exit_ext_func_mode(GPIO_DEV);
+	pnp_exit_conf_state(GPIO_DEV);
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index adcf381604..d893cf5e24 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -94,7 +94,7 @@ static void sio_init(void)
 {
 	u8 reg;
 
-	pnp_enter_ext_func_mode(SERIAL_DEV);
+	pnp_enter_conf_state(SERIAL_DEV);
 	/* We have 24MHz input. */
 	reg = pnp_read_config(SERIAL_DEV, 0x24);
 	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
@@ -104,9 +104,9 @@ static void sio_init(void)
 	/* We have all RESTOUT and even some reserved bits, too. */
 	reg = pnp_read_config(SERIAL_DEV, 0x2c);
 	pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
-	pnp_exit_ext_func_mode(SERIAL_DEV);
+	pnp_exit_conf_state(SERIAL_DEV);
 
-	pnp_enter_ext_func_mode(ACPI_DEV);
+	pnp_enter_conf_state(ACPI_DEV);
 	pnp_set_logical_device(ACPI_DEV);
 	/*
 	 * Set the delay rising time from PWROK_LP to PWROK_ST to
@@ -117,9 +117,9 @@ static void sio_init(void)
 	/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
 	reg = pnp_read_config(ACPI_DEV, 0xe4);
 	pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
-	pnp_exit_ext_func_mode(ACPI_DEV);
+	pnp_exit_conf_state(ACPI_DEV);
 
-	pnp_enter_ext_func_mode(GPIO_DEV);
+	pnp_enter_conf_state(GPIO_DEV);
 	pnp_set_logical_device(GPIO_DEV);
 	/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
 	pnp_write_config(GPIO_DEV, 0x30, 0x09);	/* Enable GPIO 2 & GPIO 5. */
@@ -129,7 +129,7 @@ static void sio_init(void)
 	pnp_write_config(GPIO_DEV, 0xe0, 0xde);	/* 1101 1110, 0 = output 1 = input */
 	pnp_write_config(GPIO_DEV, 0xe1, 0x01);	/* Set output val. */
 	pnp_write_config(GPIO_DEV, 0xe4, 0xb4);	/* Set output val (1011 0100). */
-	pnp_exit_ext_func_mode(GPIO_DEV);
+	pnp_exit_conf_state(GPIO_DEV);
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 7088f1deea..43c56778ba 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -62,7 +62,7 @@ static void early_superio_config_w83627ehg(void)
 	pnp_devfn_t dev;
 
 	dev = DUMMY_DEV;
-	pnp_enter_ext_func_mode(dev);
+	pnp_enter_conf_state(dev);
 
 	pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
 
@@ -121,7 +121,7 @@ static void early_superio_config_w83627ehg(void)
 	pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
 	pnp_set_enable(dev, 1);
 
-	pnp_exit_ext_func_mode(dev);
+	pnp_exit_conf_state(dev);
 }
 
 static void rcba_config(void)
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 878a79e9ca..8ddfdd67ac 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -126,11 +126,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
 	/* FIXME: This should be part of the Super I/O code/config. */
-	pnp_enter_ext_func_mode(SERIAL_DEV);
+	pnp_enter_conf_state(SERIAL_DEV);
 	/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
 	pnp_write_config(SERIAL_DEV, 0x24, 0);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	pnp_exit_ext_func_mode(SERIAL_DEV);
+	pnp_exit_conf_state(SERIAL_DEV);
 
 	setup_mb_resource_map();
 	console_init();
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 11e9bc0492..ec11dd6b26 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -129,11 +129,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x32);
 
-	pnp_enter_ext_func_mode(SERIAL_DEV);
+	pnp_enter_conf_state(SERIAL_DEV);
 	/* We have 24MHz input. */
 	reg = pnp_read_config(SERIAL_DEV, 0x24);
 	pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
-	pnp_exit_ext_func_mode(SERIAL_DEV);
+	pnp_exit_conf_state(SERIAL_DEV);
 
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index d8076f0b79..c2fd79858c 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -124,9 +124,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-	pnp_enter_ext_func_mode(SERIAL_DEV);
+	pnp_enter_conf_state(SERIAL_DEV);
 	pnp_write_config(SERIAL_DEV, 0x24, 0);
-	pnp_exit_ext_func_mode(SERIAL_DEV);
+	pnp_exit_conf_state(SERIAL_DEV);
 
 	setup_mb_resource_map();