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mediatek/mt8183: Correct MPU ctrl register address 

Remove unused members in emi_mpu_regs and sdram_params. Change
mpu_ctrl_d to array so the offset (0x804) for D1 is corrected.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.

Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/29251
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Huayang Duan 2018-10-23 16:05:24 +08:00 committed by Patrick Georgi
parent 0f5d7b9daf
commit bb7f4c7a4f
3 changed files with 10 additions and 25 deletions
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12
src/soc/mediatek/mt8183/emi.c
View File

@ -54,7 +54,7 @@ static u64 get_ch_rank_size(u8 chn, u8 rank)
row_bit = ((((emi_cona >> (24 - chn * 20 + rank)) & 0x01) << 2) +
((emi_cona >> (12 + chn * 16 + rank * 2)) & 0x03)) + 13;
/* data width (bytes) * 8 banks */
/* Data width (bytes) * 8 banks */
return ((u64)(1 << (row_bit + col_bit))) *
((u64)(4 >> shift_for_16bit) * 8);
}
@ -80,7 +80,7 @@ void dramc_get_rank_size(u64 *dram_rank_size)
else
ch_rank0_size = (ch0_rank0_size * 256 << 20);
/* dual rank enable */
/* Dual rank enable */
if ((emi_cona & (1 << 17)) != 0) {
if (ch0_rank1_size == 0)
ch_rank1_size = get_ch_rank_size(CHANNEL_A, RANK_1);
@ -115,7 +115,7 @@ size_t sdram_size(void)
for (int i = 0; i < RANK_MAX; i++) {
dram_size += rank_size[i];
dramc_show("rank%d size:0x%llx\n", i, rank_size[i]);
dramc_show("Rank%d size:0x%llx\n", i, rank_size[i]);
}
return dram_size;
@ -126,7 +126,7 @@ static void set_rank_info_to_conf(const struct sdram_params *params)
u8 u4value = 0;
/* CONA 17th bit 0: Disable dual rank mode
* 1: Enable dual rank mode */
1: Enable dual rank mode */
u4value = ((params->emi_cona_val & (0x1 << 17)) >> 17) ? 0 : 1;
clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 12, u4value << 12);
}
@ -249,8 +249,8 @@ static void emi_init2(const struct sdram_params *params)
{
emi_esl_setting2();
setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 1, 0x1 << 4);
setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 7, 0x1 << 4);
setbits_le32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4);
setbits_le32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4);
write32(&emi_regs->bwct0, 0x0a000705);
write32(&emi_regs->bwct0_3rd, 0x0);

21
src/soc/mediatek/mt8183/include/soc/dramc_register.h
View File

@ -936,25 +936,12 @@ check_member(chn_emi_regs, chn_emi_shf0, 0x0710);
struct emi_mpu_regs {
uint32_t mpu_ctrl;
uint32_t mpu_dbg;
uint32_t rsvd_2[62];
uint32_t mpu_sa0;
uint32_t rsvd_3[63];
uint32_t mpu_ea0;
uint32_t rsvd_4[63];
uint32_t mpu_apc0;
uint32_t rsvd_5[319];
uint32_t mpu_ctrl_d0;
uint32_t rsvd_6[63];
uint32_t rg_mask_d0;
uint32_t rsvd[511];
uint32_t mpu_ctrl_d[16];
};
check_member(emi_mpu_regs, mpu_dbg, 0x0004);
check_member(emi_mpu_regs, mpu_sa0, 0x0100);
check_member(emi_mpu_regs, mpu_ea0, 0x0200);
check_member(emi_mpu_regs, mpu_apc0, 0x0300);
check_member(emi_mpu_regs, mpu_ctrl_d0, 0x0800);
check_member(emi_mpu_regs, rg_mask_d0, 0x0900);
check_member(emi_mpu_regs, mpu_ctrl, 0x0000);
check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800);
enum {
TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT = 12,

2
src/soc/mediatek/mt8183/include/soc/emi.h
View File

@ -25,8 +25,6 @@ struct sdram_params {
u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
u8 cbt_cs[CHANNEL_MAX][RANK_MAX];
u8 cbt_mr12[CHANNEL_MAX][RANK_MAX];
s8 clk_delay;
s8 dqs_delay[CHANNEL_MAX];
u32 emi_cona_val;
u32 emi_conh_val;
u32 emi_conf_val;