Add newlines at the end of all coreboot files

Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15974
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

payloads/libpayload/arch/arm64/lib/Makefile.inc

@@ -30,4 +30,4 @@
 
 lib_access = pstate.c sysctrl.c cache.c tlb.c clock.c
 
-libc-y += $(lib_access)
+libc-y += $(lib_access)

src/drivers/intel/gma/Makefile.inc

@@ -19,4 +19,4 @@ ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c
 ifeq ($(CONFIG_VGA_ROM_RUN),y)
 ramstage-$(CONFIG_INTEL_INT15) += int15.c
 endif
-ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c
+ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c

src/drivers/spi/tpm/Makefile.inc

@@ -4,4 +4,4 @@ ifneq ($(CONFIG_CHROMEOS),y)
 bootblock-$(CONFIG_SPI_TPM) += tis.c tpm.c
 romstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
 ramstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
-endif
+endif

src/drivers/xgi/common/XGI_main.c

@@ -864,4 +864,4 @@ static void XGIfb_post_setmode(struct xgifb_video_info *xgifb_info)
 	}
 }
 
-#endif
+#endif

src/drivers/xgi/common/xgi_coreboot.h

@@ -284,4 +284,4 @@ void pci_set_drvdata(struct pci_dev *pdev, struct xgifb_video_info *data);
 int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info);
 int xgifb_modeset(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info);
 
-#endif
+#endif

src/drivers/xgi/z9s/Makefile.inc

@@ -1 +1 @@
-ramstage-$(CONFIG_DRIVERS_XGI_Z9S) += z9s.c
+ramstage-$(CONFIG_DRIVERS_XGI_Z9S) += z9s.c

src/mainboard/asus/kcma-d8/acpi_tables.c

@@ -106,4 +106,4 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
 	current += 8;
 
 	return current;
-}
+}

src/mainboard/asus/kcma-d8/spd_notes.txt

@@ -43,4 +43,4 @@ After that, there's a cascade of small FETs and resistors in that region, eventu
 SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW.
 VSBGATE# is reset on every assertion of PWRGOOD.
 
-Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.
+Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.

src/mainboard/asus/kfsn4-dre/bootblock.c

@@ -78,4 +78,4 @@ void bootblock_mainboard_init(void)
 		 */
 #endif
 	}
-}
+}

src/mainboard/asus/kfsn4-dre_k8/bootblock.c

@@ -78,4 +78,4 @@ void bootblock_mainboard_init(void)
 		 */
 #endif
 	}
-}
+}

src/mainboard/asus/kgpe-d16/acpi_tables.c

@@ -106,4 +106,4 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
 	current += 8;
 
 	return current;
-}
+}

src/mainboard/asus/kgpe-d16/spd_notes.txt

@@ -43,4 +43,4 @@ After that, there's a cascade of small FETs and resistors in that region, eventu
 SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW.
 VSBGATE# is reset on every assertion of PWRGOOD.
 
-Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.
+Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.

src/mainboard/google/ninja/acpi_tables.c

@@ -61,4 +61,4 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current = acpi_madt_irq_overrides(current);
 
 	return current;
-}
+}

src/mainboard/google/veyron/sdram_inf/sdram-unused.inc

@@ -1,3 +1,3 @@
 {
 	.dramtype= UNUSED
-},
+},

src/mainboard/google/veyron_brain/sdram_inf/sdram-unused.inc

@@ -1,3 +1,3 @@
 {
 	.dramtype= UNUSED
-},
+},

src/mainboard/google/veyron_danger/sdram_inf/sdram-unused.inc

@@ -1,3 +1,3 @@
 {
 	.dramtype= UNUSED
-},
+},

src/mainboard/google/veyron_emile/sdram_inf/sdram-unused.inc

@@ -1,3 +1,3 @@
 {
 	.dramtype= UNUSED
-},
+},

src/mainboard/google/veyron_mickey/sdram_inf/sdram-unused.inc

@@ -1,3 +1,3 @@
 {
 	.dramtype= UNUSED
-},
+},

src/mainboard/google/veyron_rialto/sdram_inf/sdram-unused.inc

@@ -1,3 +1,3 @@
 {
 	.dramtype= UNUSED
-},
+},

src/mainboard/google/veyron_romy/sdram_inf/sdram-unused.inc

@@ -1,3 +1,3 @@
 {
 	.dramtype= UNUSED
-},
+},

src/mainboard/intel/camelbackmountain_fsp/Makefile.inc

@@ -13,4 +13,4 @@
 ## GNU General Public License for more details.
 ##
 
-ramstage-y += irqroute.c
+ramstage-y += irqroute.c

src/mainboard/intel/stargo2/acpi/ec.asl

@@ -6,4 +6,4 @@
  * This file is included by lpc.asl in the southbridge directory.
  * It is intended to be used to include any embedded controller
  * specific ASL.
- */
+ */

src/mainboard/lenovo/t400/cmos.default

@@ -14,4 +14,4 @@ power_management_beeps=Enable
 low_battery_beep=Enable
 sata_mode=AHCI
 hybrid_graphics_mode=Integrated Only
-gfx_uma_size=32M
+gfx_uma_size=32M

src/mainboard/lenovo/t420/cmos.default

@@ -14,4 +14,4 @@ fn_ctrl_swap=Disable
 sticky_fn=Disable
 trackpoint=Enable
 hyper_threading=Enable
-hybrid_graphics_mode=Integrated Only
+hybrid_graphics_mode=Integrated Only

src/mainboard/lenovo/t420s/cmos.default

@@ -14,4 +14,4 @@ fn_ctrl_swap=Disable
 sticky_fn=Disable
 trackpoint=Enable
 hyper_threading=Enable
-hybrid_graphics_mode=Integrated Only
+hybrid_graphics_mode=Integrated Only

src/mainboard/lenovo/t520/cmos.default

@@ -15,4 +15,4 @@ sticky_fn=Disable
 trackpoint=Enable
 hyper_threading=Enable
 backlight=Both
-hybrid_graphics_mode=Integrated Only
+hybrid_graphics_mode=Integrated Only

src/mainboard/lenovo/t530/cmos.default

@@ -15,4 +15,4 @@ sticky_fn=Disable
 trackpoint=Enable
 hyper_threading=Enable
 backlight=Both
-hybrid_graphics_mode=Integrated Only
+hybrid_graphics_mode=Integrated Only

src/mainboard/lenovo/x200/cmos.default

@@ -13,4 +13,4 @@ sticky_fn=Disable
 power_management_beeps=Enable
 low_battery_beep=Enable
 sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=32M

src/mainboard/siemens/mc_bdx1/Makefile.inc

@@ -13,4 +13,4 @@
 ## GNU General Public License for more details.
 ##
 
-ramstage-y += irqroute.c
+ramstage-y += irqroute.c

src/northbridge/amd/amdk8/thermal_mixin.asl

@@ -282,4 +282,4 @@ ThermalZone (K8T3) {
 		Add(Local0, K8TEMP_CRITICAL_ADD, Local0)
 		Return (Multiply(Local0, 10))
 	}
-}
+}

src/soc/intel/fsp_broadwell_de/northcluster.c

@@ -153,4 +153,4 @@ static const struct pci_driver nc_driver_es2 __pci_driver = {
 	.ops    = &nc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.device = SOC_DEVID_ES2,
-};
+};

src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc

@@ -1,3 +1,3 @@
 romstage-y += romstage.c
 
-$(obj)/soc/intel/fsp_broadwell_de/romstage/romstage.romstage.o : $(obj)/build.h
+$(obj)/soc/intel/fsp_broadwell_de/romstage/romstage.romstage.o : $(obj)/build.h

src/soc/intel/skylake/acpi/scs.asl

@@ -140,4 +140,4 @@ Device (SDXC)
 		}
 	}
 }
-#endif
+#endif

src/southbridge/amd/sb700/spi.c

@@ -141,4 +141,4 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
 	}
 
 	return 0;
-}
+}

src/southbridge/amd/sb700/spi.h

@@ -14,4 +14,4 @@
  */
 
 int spi_claim_bus(struct spi_slave *slave);
-void spi_release_bus(struct spi_slave *slave);
+void spi_release_bus(struct spi_slave *slave);

src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl

@@ -86,4 +86,4 @@ Scope (\_SB.PCI0.LPCB)
 		Store (0x1, GIOS) // INPUT
 		Store (0x1, GINV) // INVERT
 	}
-}
+}

src/southbridge/nvidia/ck804/early_setup_car.c

@@ -379,4 +379,4 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
         /* The default value for CK804 is good. */
         /* Set VFSMAF (VID/FID System Management Action Field) to 2. */
-}
+}

util/broadcom/Makefile.inc

@@ -1 +1 @@
-subdirs-$(CONFIG_SOC_BROADCOM_CYGNUS) += secimage
+subdirs-$(CONFIG_SOC_BROADCOM_CYGNUS) += secimage