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Set the ROMSIZE as 4MB. 

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2010-12-14 01:47:18 +00:00 committed by Zheng Bao
parent dd6619f5e9
commit bb9bceebc1
3 changed files with 16 additions and 4 deletions
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5
src/southbridge/amd/sb600/Kconfig
View File

@ -23,6 +23,11 @@ config SOUTHBRIDGE_AMD_SB600
select HAVE_USBDEBUG
select TINY_BOOTBLOCK
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/sb600/bootblock.c"
depends on SOUTHBRIDGE_AMD_SB600
config EHCI_BAR
hex
default 0xfef00000 if SOUTHBRIDGE_AMD_SB600

5
src/southbridge/amd/sb700/Kconfig
View File

@ -23,6 +23,11 @@ config SOUTHBRIDGE_AMD_SB700
select HAVE_USBDEBUG
select TINY_BOOTBLOCK
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/sb700/bootblock.c"
depends on SOUTHBRIDGE_AMD_SB700
config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
bool
default n

10
src/southbridge/amd/sb700/bootblock.c
View File

@ -23,12 +23,12 @@
#include <device/pci_ids.h>
/*
* Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF.
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
*
* Hardware should enable LPC ROM by pin straps. This function does not
* handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
*
* The SB700 power-on default is to map 256K ROM space.
* The SB700 power-on default is to map 512K ROM space.
*
* Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00,
* PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14.
@ -39,7 +39,7 @@ static void sb700_enable_rom(void)
device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
PCI_DEVICE_ID_ATI_SB700_LPC), 0);
PCI_DEVICE_ID_ATI_SB700_LPC), 0);
/* Decode variable LPC ROM address ranges 1 and 2. */
reg8 = pci_read_config8(dev, 0x48);
@ -57,8 +57,10 @@ static void sb700_enable_rom(void)
* Enable LPC ROM range start at:
* 0xfff8(0000): 512KB
* 0xfff0(0000): 1MB
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
/* Enable LPC ROM range end at 0xffff(ffff). */
pci_write_config16(dev, 0x6e, 0xffff);
}