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Here is just a little and simple patch to get the MX25L3205D working. 

I've tested and verified the chip myself, and it seems to work
everything like supposted, since Carl-Daniel has patched flashrom to
use the read funktion on verifying. 

"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... 
Serial flash segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
MX25L3205 found at physical address 0xffc00000.
Flash part is MX25L3205 (4096 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
benchvice flashrom # ls -l test.4mb
-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Harald Gutmann 2008-01-22 16:03:19 +00:00 committed by Carl-Daniel Hailfinger
parent a6941beb43
commit bb9c1aa54e
1 changed files with 2 additions and 0 deletions
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2
util/flashrom/flashchips.c
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@ -54,6 +54,8 @@ struct flashchip flashchips[] = {
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
{"MX25L8005", MX_ID, MX_25L8005, 1024, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
{"MX25L3205", MX_ID, MX_25L3205, 4096, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
{"SST25VF040B", SST_ID, SST_25VF040B, 512, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
{"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,