Let Geode GX2 use geode_post_code.h just like Geode LX
Also clean up gx2def.h and geode_post_code.h a little. abuild tested and boot tested on a Wyse S50. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
Peter Stuge
parent
7a4952a54f
commit
bba0d76952
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@ -37,7 +37,6 @@
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#define POST_sioTest (0x00E)
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#define POST_pcATjunk (0x00F)
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#define POST_intTable (0x010)
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#define POST_memInfo (0x011)
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#define POST_romCopy (0x012)
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@ -55,7 +54,6 @@
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#define POST_GLIUInit (0x01E)
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#define POST_BootFailed (0x01F)
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#define POST_CPU_ID (0x020)
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#define POST_COUNTERBROKEN (0x021)
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#define POST_DIFF_DIMMS (0x022)
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@ -67,26 +65,21 @@
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#define POST_CPU_STEPPING (0x028)
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#define POST_CPU_DM_BIST_FAILURE (0x029)
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#define POST_CPU_FLAGS (0x02A)
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#define POST_CHIPSET_ID (0x02b)
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#define POST_CHIPSET_ID_PASS (0x02c)
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#define POST_CHIPSET_ID_FAIL (0x02d)
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#define POST_CHIPSET_ID (0x02B)
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#define POST_CHIPSET_ID_PASS (0x02C)
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#define POST_CHIPSET_ID_FAIL (0x02D)
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#define POST_CPU_ID_GOOD (0x02E)
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#define POST_CPU_ID_FAIL (0x02F)
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/* PCI config*/
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#define P80_PCICFG (0x030)
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/* PCI io*/
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#define P80_PCIIO (0x040)
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/* PCI memory*/
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#define P80_PCIMEM (0x050)
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/* SIO*/
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#define P80_SIO (0x060)
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@ -102,14 +95,13 @@
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#define ERROR_NO_DIMMS (0x077)
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#define ERROR_DIFF_DIMMS (0x078)
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#define ERROR_BAD_LATENCY (0x079)
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#define ERROR_SET_PAGE (0x07a)
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#define ERROR_DENSITY_DIMM (0x07b)
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#define ERROR_UNSUPPORTED_DIMM (0x07c)
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#define ERROR_BANK_SET (0x07d)
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#define ERROR_SET_PAGE (0x07A)
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#define ERROR_DENSITY_DIMM (0x07B)
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#define ERROR_UNSUPPORTED_DIMM (0x07C)
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#define ERROR_BANK_SET (0x07D)
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#define POST_MEM_SETUP_GOOD (0x07E)
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#define POST_MEM_SETUP_FAIL (0x07F)
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#define POST_UserPreInit (0x080)
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#define POST_UserPostInit (0x081)
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#define POST_Equipment_check (0x082)
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@ -120,12 +112,11 @@
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#define POST_CPU_IM_TAG_BIST_FAILURE (0x087)
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#define POST_CPU_IM_DATA_BIST_FAILURE (0x088)
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#define POST_CPU_FPU_BIST_FAILURE (0x089)
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#define POST_CPU_BTB_BIST_FAILURE (0x08a)
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#define POST_CPU_EX_BIST_FAILURE (0x08b)
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#define POST_Chipset_PI_Test_Fail (0x08c)
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#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d)
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#define POST_BIT_CLK_Fail (0x08e)
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#define POST_CPU_BTB_BIST_FAILURE (0x08A)
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#define POST_CPU_EX_BIST_FAILURE (0x08B)
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#define POST_Chipset_PI_Test_Fail (0x08C)
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#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D)
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#define POST_BIT_CLK_Fail (0x08E)
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#define POST_STACK_SETUP (0x090)
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#define POST_CPU_PF_BIST_FAILURE (0x091)
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@ -137,7 +128,6 @@
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#define POST_STACK_SETUP_PASS (0x09E)
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#define POST_STACK_SETUP_FAIL (0x09F)
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#define POST_PLL_INIT (0x0A0)
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#define POST_PLL_MANUAL (0x0A1)
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#define POST_PLL_STRAP (0x0A2)
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@ -146,7 +136,6 @@
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#define POST_PLL_MEM_FAIL (0x0A5)
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#define POST_PLL_CPU_VER_FAIL (0x0A6)
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#define POST_MEM_TESTMEM (0x0B0)
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#define POST_MEM_TESTMEM1 (0x0B1)
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#define POST_MEM_TESTMEM2 (0x0B2)
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@ -155,7 +144,6 @@
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#define POST_MEM_TESTMEM_PASS (0x0BE)
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#define POST_MEM_TESTMEM_FAIL (0x0BF)
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#define POST_SECUROM_SECBOOT_START (0x0C0)
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#define POST_SECUROM_BOOTSRCSETUP (0x0C1)
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#define POST_SECUROM_REMAP_FAIL (0x0C2)
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@ -174,7 +162,6 @@
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#define POST_RCONFInitError (0x0CE)
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#define POST_CacheInitError (0x0CF)
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#define POST_ROM_PREUNCOMPRESS (0x0D0)
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#define POST_ROM_UNCOMPRESS (0x0D1)
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#define POST_ROM_SMM_INIT (0x0D2)
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@ -187,11 +174,9 @@
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#define POST_ROM_TVINIT (0x0D9)
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#define POST_ROM_POSTUNCOMPRESS (0x0DE)
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#define P80_CHIPSET_INIT (0x0E0)
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#define POST_PreChipsetInit (0x0E1)
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#define POST_LateChipsetInit (0x0E2)
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#define POST_NORTHB_INIT (0x0E8)
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#define POST_INTR_SEG_JUMP (0x0F0)
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@ -503,187 +503,6 @@
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#define CHIPSET_DEV_NUM 15
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#define IDSEL_BASE 11 // bit 11 = device 1
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/* standard AMD post definitions -- might as well use them. */
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#define POST_Output_Port (0x080) /* port to write post codes to*/
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#define POST_preSioInit (0x000) /* geode.asm*/
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#define POST_clockInit (0x001) /* geode.asm*/
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#define POST_CPURegInit (0x002) /* geode.asm*/
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#define POST_UNREAL (0x003) /* geode.asm*/
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#define POST_CPUMemRegInit (0x004) /* geode.asm*/
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#define POST_CPUTest (0x005) /* geode.asm*/
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#define POST_memSetup (0x006) /* geode.asm*/
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#define POST_memSetUpStack (0x007) /* geode.asm*/
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#define POST_memTest (0x008) /* geode.asm*/
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#define POST_shadowRom (0x009) /* geode.asm*/
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#define POST_memRAMoptimize (0x00A) /* geode.asm*/
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#define POST_cacheInit (0x00B) /* geode.asm*/
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#define POST_northBridgeInit (0x00C) /* geode.asm*/
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#define POST_chipsetInit (0x00D) /* geode.asm*/
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#define POST_sioTest (0x00E) /* geode.asm*/
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#define POST_pcATjunk (0x00F) /* geode.asm*/
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#define POST_intTable (0x010) /* geode.asm*/
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#define POST_memInfo (0x011) /* geode.asm*/
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#define POST_romCopy (0x012) /* geode.asm*/
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#define POST_PLLCheck (0x013) /* geode.asm*/
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#define POST_keyboardInit (0x014) /* geode.asm*/
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#define POST_cpuCacheOff (0x015) /* geode.asm*/
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#define POST_BDAInit (0x016) /* geode.asm*/
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#define POST_pciScan (0x017) /* geode.asm*/
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#define POST_optionRomInit (0x018) /* geode.asm*/
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#define POST_ResetLimits (0x019) /* geode.asm*/
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#define POST_summary_screen (0x01A) /* geode.asm*/
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#define POST_Boot (0x01B) /* geode.asm*/
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#define POST_SystemPreInit (0x01C) /* geode.asm*/
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#define POST_ClearRebootFlag (0x01D) /* geode.asm*/
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#define POST_GLIUInit (0x01E) /* geode.asm*/
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#define POST_BootFailed (0x01F) /* geode.asm*/
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#define POST_CPU_ID (0x020) /* cpucpuid.asm*/
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#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/
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#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/
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#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/
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#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/
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#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/
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#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/
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#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/
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#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/
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#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/
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#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/
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#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/
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#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/
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#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/
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#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/
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#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/
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/* PCI config*/
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#define P80_PCICFG (0x030) /* pcispace.asm*/
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/* PCI io*/
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#define P80_PCIIO (0x040) /* pcispace.asm*/
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/* PCI memory*/
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#define P80_PCIMEM (0x050) /* pcispace.asm*/
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/* SIO*/
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#define P80_SIO (0x060) /* *sio.asm*/
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/* Memory Setp*/
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#define P80_MEM_SETUP (0x070) /* docboot meminit*/
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#define POST_MEM_SETUP (0x070) /* memsize.asm*/
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#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/
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#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/
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#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/
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#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/
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#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/
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#define POST_MEM_ENABLE (0x076) /* memsize.asm*/
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#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/
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#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/
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#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/
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#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/
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#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/
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#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/
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#define ERROR_BANK_SET (0x07d) /* memsize.asm*/
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#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/
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#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/
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#define POST_UserPreInit (0x080) /* geode.asm*/
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#define POST_UserPostInit (0x081) /* geode.asm*/
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#define POST_Equipment_check (0x082) /* geode.asm*/
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#define POST_InitNVRAMBX (0x083) /* geode.asm*/
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#define POST_NoPIRTable (0x084) /* pci.asm*/
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#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/
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#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/
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#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/
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#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/
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#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/
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#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/
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#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/
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#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/
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#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/
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#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/
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#define POST_STACK_SETUP (0x090) /* memstack.asm*/
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#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/
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#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/
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#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/
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#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/
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#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/
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#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/
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#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/
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#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/
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#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/
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#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/
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#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/
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#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/
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#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/
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#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/
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#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/
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#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/
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#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/
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#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/
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#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/
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#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/
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#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/
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#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/
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#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/
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#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/
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#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/
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#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/
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#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/
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#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/
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#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/
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#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/
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#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/
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#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/
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#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/
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#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/
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#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/
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#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/
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#define POST_RCONFInitError (0x0CE) /* cache.asm*/
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#define POST_CacheInitError (0x0CF) /* cache.asm*/
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#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/
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#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/
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#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/
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#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/
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#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/
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#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/
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#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/
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#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/
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#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/
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#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/
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#define POST_ROM_POSTUNCOMPRESS (0x0DE)
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#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/
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#define POST_PreChipsetInit (0x0E1) /* geode.asm*/
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#define POST_LateChipsetInit (0x0E2) /* geode.asm*/
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#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/
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#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/
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/* */
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/* SB LBAR IO + MEMORY MAP*/
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/* */
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#include <cpu/amd/geode_post_code.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#include <cpu/amd/geode_post_code.h>
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#include "southbridge/amd/cs5535/cs5535.h"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#include <cpu/amd/geode_post_code.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#include <cpu/amd/geode_post_code.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include "cpu/x86/bist.h"
|
||||
#include "cpu/x86/msr.h"
|
||||
#include <cpu/amd/gx2def.h>
|
||||
#include <cpu/amd/geode_post_code.h>
|
||||
|
||||
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
|
||||
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include "chip.h"
|
||||
#include "northbridge/amd/gx2/northbridge.h"
|
||||
#include <cpu/amd/gx2def.h>
|
||||
#include <cpu/amd/geode_post_code.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include "southbridge/amd/cs5535/cs5535.h"
|
||||
|
|
|
|||
Loading…
Reference in New Issue