soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register

Clang complains about this.

Change-Id: I2d761d2fa946f171033220ab7b2e399cf359782a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/cavium/cn81xx/cpu.c

@@ -35,7 +35,7 @@ void secondary_cpu_init(size_t core_id)
 
 size_t cpu_self_get_core_id(void)
 {
-	u32 mpidr_el1;
+	u64 mpidr_el1;
 	asm("mrs %0, MPIDR_EL1\n\t" : "=r" (mpidr_el1) :: "memory");
 
 	/* Core is 4 bits from AFF0 and rest from AFF1 */