google/asuka: Add as a variant of glados
Add google/asuka (Dell Chromebook 13 3380) as a variant of
glados Skylake reference board:
- add asuka-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]
Test: build/boot google/asuka, verify correct functionality
Change-Id: I591578fea2514a28c75177835807c3f250904577
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27421
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier
Martin Roth
parent
ec975b0a4f
commit
bba1ee070d
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@ -36,6 +36,7 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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string
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default "Asuka" if BOARD_GOOGLE_ASUKA
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default "Caroline" if BOARD_GOOGLE_CAROLINE
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default "Cave" if BOARD_GOOGLE_CAVE
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default "Chell" if BOARD_GOOGLE_CHELL
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@ -49,6 +50,7 @@ config MAINBOARD_FAMILY
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config VARIANT_DIR
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string
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default "asuka" if BOARD_GOOGLE_ASUKA
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default "caroline" if BOARD_GOOGLE_CAROLINE
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default "cave" if BOARD_GOOGLE_CAVE
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default "chell" if BOARD_GOOGLE_CHELL
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@ -58,6 +60,7 @@ config VARIANT_DIR
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config DEVICETREE
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string
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default "variants/asuka/devicetree.cb" if BOARD_GOOGLE_ASUKA
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default "variants/caroline/devicetree.cb" if BOARD_GOOGLE_CAROLINE
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default "variants/cave/devicetree.cb" if BOARD_GOOGLE_CAVE
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default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL
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@ -93,6 +96,7 @@ config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
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config GBB_HWID
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string
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depends on CHROMEOS
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default "ASUKA TEST 2547" if BOARD_GOOGLE_ASUKA
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default "CAROLINE TEST 0958" if BOARD_GOOGLE_CAROLINE
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default "CAVE TEST 9629" if BOARD_GOOGLE_CAVE
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default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL
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@ -1,5 +1,12 @@
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comment "Glados"
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config BOARD_GOOGLE_ASUKA
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bool "-> Asuka (Dell Chromebook 13 3380)"
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select BOARD_GOOGLE_BASEBOARD_GLADOS
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select DRIVERS_GENERIC_MAX98357A
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select EXCLUDE_NATIVE_SD_INTERFACE
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select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS
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config BOARD_GOOGLE_CAROLINE
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bool "-> Caroline (Samsung Chromebook Pro)"
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select BOARD_GOOGLE_BASEBOARD_GLADOS
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@ -0,0 +1,41 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2015 Google Inc.
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## Copyright (C) 2015 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += variant.c
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ramstage-y += variant.c
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SPD_BIN = $(obj)/spd.bin
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SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Single Channel 2GB
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SPD_SOURCES += hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0001 Dual Channel 4GB
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SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0010 Single Channel 2GB
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SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0011 Dual Channel 4GB
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SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0100 Single Channel 2GB
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SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0101 Dual Channel 4GB
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd ROM data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do printf $$(printf '\%o' 0x$$c); \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := spd
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@ -0,0 +1,6 @@
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Vendor name: Google
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Board name: Asuka (Dell Chromebook 13 3380)
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Binary file not shown.
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@ -0,0 +1,288 @@
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chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable DPTF
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register "dptf_enable" = "1"
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# FSP Configuration
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "SmbusEnable" = "1"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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register "SaGv" = "3"
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register "SerialIrqConfigSirqEnable" = "1"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "4" # 4s
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register "PmConfigSlpSusMinAssert" = "3" # 4s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 5 Domains
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_RING]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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# Enable Root port 1
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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# RP 1 uses SRCCLKREQ1#
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register "PcieRpClkReqNumber[0]" = "1"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Card Reader
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (board)
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register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # PIC MCU
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register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board)
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart0] = PchSerialIoPci,
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[PchSerialIoIndexUart1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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# PL2 override 25W
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register "tdp_pl2_override" = "25"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
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device i2c 10 on end
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end
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end # I2C #0
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device pci 15.1 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
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register "wake" = "GPE0_DW0_05"
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device i2c 15 on end
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end
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end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 off end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.2 on
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chip drivers/i2c/nau8825
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"
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register "jkdet_enable" = "1"
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register "jkdet_pull_enable" = "0" # R389
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register "jkdet_polarity" = "1" # ActiveLow
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register "vref_impedance" = "2" # 125kOhm
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register "micbias_voltage" = "6" # 2.754
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register "sar_threshold_num" = "4"
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register "sar_threshold[0]" = "0x08"
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register "sar_threshold[1]" = "0x12"
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register "sar_threshold[2]" = "0x26"
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register "sar_threshold[3]" = "0x73"
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register "sar_hysteresis" = "0"
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register "sar_voltage" = "6"
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register "sar_compare_time" = "1" # 1us
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register "sar_sampling_time" = "1" # 4us
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register "short_key_debounce" = "3" # 30ms
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register "jack_insert_debounce" = "7" # 512ms
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register "jack_eject_debounce" = "0"
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device i2c 1a on end
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end
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end # I2C #4
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device pci 1c.0 on
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chip drivers/intel/wifi
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register "wake" = "GPE0_DW0_16"
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device pci 00.0 on end
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end
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end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1e.0 on end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1e.4 on end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 off end # SDCard
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on
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chip drivers/generic/max98357a
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
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register "sdmode_delay" = "5"
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device generic 0 on end
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end
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end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_CPU_PASSIVE 101
|
||||
#define DPTF_CPU_CRITICAL 106
|
||||
|
||||
#define DPTF_TSR0_SENSOR_ID 0
|
||||
#define DPTF_TSR0_SENSOR_NAME "TMP432_Memory"
|
||||
#define DPTF_TSR0_PASSIVE 74
|
||||
#define DPTF_TSR0_CRITICAL 79
|
||||
#define DPTF_TSR0_ACTIVE_AC0 120
|
||||
#define DPTF_TSR0_ACTIVE_AC1 110
|
||||
#define DPTF_TSR0_ACTIVE_AC2 47
|
||||
#define DPTF_TSR0_ACTIVE_AC3 44
|
||||
#define DPTF_TSR0_ACTIVE_AC4 41
|
||||
#define DPTF_TSR0_ACTIVE_AC5 38
|
||||
#define DPTF_TSR0_ACTIVE_AC6 35
|
||||
|
||||
#define DPTF_TSR1_SENSOR_ID 1
|
||||
#define DPTF_TSR1_SENSOR_NAME "TMP432_PCH"
|
||||
#define DPTF_TSR1_PASSIVE 72
|
||||
#define DPTF_TSR1_CRITICAL 77
|
||||
#define DPTF_TSR1_ACTIVE_AC0 45
|
||||
#define DPTF_TSR1_ACTIVE_AC1 42
|
||||
#define DPTF_TSR1_ACTIVE_AC2 39
|
||||
#define DPTF_TSR1_ACTIVE_AC3 36
|
||||
#define DPTF_TSR1_ACTIVE_AC4 33
|
||||
|
||||
#define DPTF_TSR2_SENSOR_ID 2
|
||||
#define DPTF_TSR2_SENSOR_NAME "TMP432_Battery"
|
||||
#define DPTF_TSR2_PASSIVE 67
|
||||
#define DPTF_TSR2_CRITICAL 72
|
||||
|
||||
#define DPTF_ENABLE_CHARGER
|
||||
#define DPTF_ENABLE_FAN_CONTROL
|
||||
#define DPTF_ENABLE_FAN_CONTROL_TSR1
|
||||
|
||||
/* Charger performance states, board-specific values from charger and EC */
|
||||
Name (CHPS, Package () {
|
||||
Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
|
||||
Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
|
||||
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
|
||||
Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
|
||||
})
|
||||
|
||||
#ifdef DPTF_ENABLE_FAN_CONTROL
|
||||
/* DFPS: Fan Performance States */
|
||||
Name (DFPS, Package () {
|
||||
0, // Revision
|
||||
/*
|
||||
* TODO : Need to update this Table after characterization.
|
||||
* These are initial reference values.
|
||||
*/
|
||||
/* Control, Trip Point, Speed, NoiseLevel, Power */
|
||||
Package () {100, 0xFFFFFFFF, 4986, 220, 2200},
|
||||
Package () {90, 0xFFFFFFFF, 4804, 180, 1800},
|
||||
Package () {80, 0xFFFFFFFF, 4512, 145, 1450},
|
||||
Package () {70, 0xFFFFFFFF, 4204, 115, 1150},
|
||||
Package () {60, 0xFFFFFFFF, 3838, 90, 900},
|
||||
Package () {50, 0xFFFFFFFF, 3402, 65, 650},
|
||||
Package () {40, 0xFFFFFFFF, 2904, 45, 450},
|
||||
Package () {30, 0xFFFFFFFF, 2337, 30, 300},
|
||||
Package () {20, 0xFFFFFFFF, 1608, 15, 150},
|
||||
Package () {10, 0xFFFFFFFF, 800, 10, 100},
|
||||
Package () {0, 0xFFFFFFFF, 0, 0, 50}
|
||||
})
|
||||
|
||||
Name (DART, Package () {
|
||||
/* Fan effect on CPU */
|
||||
0, // Revision
|
||||
Package () {
|
||||
/*
|
||||
* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
|
||||
* AC7, AC8, AC9
|
||||
*/
|
||||
\_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0
|
||||
},
|
||||
Package () {
|
||||
\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0
|
||||
},
|
||||
Package () {
|
||||
\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 79, 66, 50, 41, 39, 0,
|
||||
0, 0, 0, 0
|
||||
}
|
||||
})
|
||||
#endif
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 0 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 10, 0, 0, 0, 0 },
|
||||
|
||||
#ifdef DPTF_ENABLE_CHARGER
|
||||
/* Charger Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 10, 0, 0, 0, 0 },
|
||||
#endif
|
||||
|
||||
/* CPU Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
3000, /* PowerLimitMinimum */
|
||||
15000, /* PowerLimitMaximum */
|
||||
28000, /* TimeWindowMinimum */
|
||||
28000, /* TimeWindowMaximum */
|
||||
100 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
25000, /* PowerLimitMinimum */
|
||||
25000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
100 /* StepSize */
|
||||
}
|
||||
})
|
||||
|
|
@ -0,0 +1,238 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* EC in RW */
|
||||
#define GPIO_EC_IN_RW GPP_C6
|
||||
|
||||
/* BIOS Flash Write Protect */
|
||||
#define GPIO_PCH_WP GPP_C23
|
||||
|
||||
/* Memory configuration board straps */
|
||||
#define GPIO_MEM_CONFIG_0 GPP_C12
|
||||
#define GPIO_MEM_CONFIG_1 GPP_C13
|
||||
#define GPIO_MEM_CONFIG_2 GPP_C14
|
||||
#define GPIO_MEM_CONFIG_3 GPP_C15
|
||||
|
||||
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
||||
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||
|
||||
/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
|
||||
#define GPE_WLAN_WAKE GPE0_DW0_16
|
||||
|
||||
/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
|
||||
#define GPE_TOUCHPAD_WAKE GPE0_DW0_05
|
||||
|
||||
/* Input device interrupt configuration */
|
||||
#define TOUCHPAD_INT_L GPP_B3_IRQ
|
||||
#define TOUCHSCREEN_INT_L GPP_E7_IRQ
|
||||
#define MIC_INT_L GPP_F10_IRQ
|
||||
|
||||
/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
|
||||
#define EC_SCI_GPI GPE0_DW2_16
|
||||
#define EC_SMI_GPI GPP_E15
|
||||
|
||||
/*
|
||||
* GPP_E3 is AUDIO_DB_ID.
|
||||
* It is a dual purpose GPIO, used for Audio Daughter
|
||||
* Board Identification & to control the shutdown mode pin
|
||||
* of the Maxim amp.
|
||||
*/
|
||||
#define AUDIO_DB_ID GPP_E3
|
||||
|
||||
#ifndef __ACPI__
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
|
||||
/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
|
||||
/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
|
||||
/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
|
||||
/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),
|
||||
/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10),
|
||||
/* EC_HID_INT */ PAD_CFG_NC(GPP_A11),
|
||||
/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12),
|
||||
/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14),
|
||||
/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||
/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
|
||||
/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17),
|
||||
/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18),
|
||||
/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
|
||||
/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20),
|
||||
/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21),
|
||||
/* GYRO_INT */ PAD_CFG_NC(GPP_A22),
|
||||
/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
|
||||
/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
|
||||
/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
|
||||
/* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),
|
||||
/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
|
||||
/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4),
|
||||
/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
|
||||
/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
|
||||
/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7),
|
||||
/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES),
|
||||
/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9),
|
||||
/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
|
||||
/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),
|
||||
/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),
|
||||
/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
|
||||
/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
|
||||
/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17),
|
||||
/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
|
||||
/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19),
|
||||
/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20),
|
||||
/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21),
|
||||
/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22),
|
||||
/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
|
||||
/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
|
||||
/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3),
|
||||
/* SML0DATA */ PAD_CFG_NC(GPP_C4),
|
||||
/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
|
||||
/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),
|
||||
/* USB_CTL */ PAD_CFG_NC(GPP_C7),
|
||||
/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
|
||||
/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
|
||||
/* NFC_RST* */ PAD_CFG_NC(GPP_C10),
|
||||
/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11),
|
||||
/* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
|
||||
/* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
|
||||
/* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
|
||||
/* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
|
||||
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
|
||||
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
|
||||
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),
|
||||
/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
|
||||
/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0),
|
||||
/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1),
|
||||
/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2),
|
||||
/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3),
|
||||
/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4),
|
||||
/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5),
|
||||
/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),
|
||||
/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
|
||||
/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
|
||||
/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9),
|
||||
/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12),
|
||||
/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13),
|
||||
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
|
||||
/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15),
|
||||
/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16),
|
||||
/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17),
|
||||
/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18),
|
||||
/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21),
|
||||
/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22),
|
||||
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
|
||||
/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
|
||||
/* SSD_PEDET */ PAD_CFG_NC(GPP_E2),
|
||||
/* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
|
||||
/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4),
|
||||
/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
|
||||
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
|
||||
/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
|
||||
/* SATALED# */ PAD_CFG_NC(GPP_E8),
|
||||
/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||
/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||
/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||
/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
|
||||
/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
|
||||
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
|
||||
/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
|
||||
/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
|
||||
/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
|
||||
/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
|
||||
/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
|
||||
/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
|
||||
/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
|
||||
/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
|
||||
/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
|
||||
/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
|
||||
/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
|
||||
/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),
|
||||
/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),
|
||||
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
/* SD_CMD */ PAD_CFG_NC(GPP_G0),
|
||||
/* SD_DATA0 */ PAD_CFG_NC(GPP_G1),
|
||||
/* SD_DATA1 */ PAD_CFG_NC(GPP_G2),
|
||||
/* SD_DATA2 */ PAD_CFG_NC(GPP_G3),
|
||||
/* SD_DATA3 */ PAD_CFG_NC(GPP_G4),
|
||||
/* SD_CD# */ PAD_CFG_NC(GPP_G5),
|
||||
/* SD_CLK */ PAD_CFG_NC(GPP_G6),
|
||||
/* SD_WP */ PAD_CFG_NC(GPP_G7),
|
||||
/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* GPD7 */ PAD_CFG_NC(GPD7),
|
||||
/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9),
|
||||
/* PM_SLP_S5# */ PAD_CFG_NC(GPD10),
|
||||
/* LANPHYC */ PAD_CFG_NC(GPD11),
|
||||
};
|
||||
|
||||
/* Early pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <baseboard/variant.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
|
||||
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||
{
|
||||
/* DQ byte map */
|
||||
const u8 dq_map[2][12] = {
|
||||
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
|
||||
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
|
||||
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
|
||||
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
|
||||
/* DQS CPU<>DRAM map */
|
||||
const u8 dqs_map[2][8] = {
|
||||
{ 0, 1, 3, 2, 6, 5, 4, 7 },
|
||||
{ 2, 3, 0, 1, 6, 7, 4, 5 } };
|
||||
|
||||
/* Rcomp resistor */
|
||||
const u16 RcompResistor[3] = { 200, 81, 162 };
|
||||
|
||||
/* Rcomp target */
|
||||
const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
|
||||
|
||||
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
|
||||
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
|
||||
memcpy(pei_data->RcompResistor, RcompResistor,
|
||||
sizeof(RcompResistor));
|
||||
memcpy(pei_data->RcompTarget, RcompTarget,
|
||||
sizeof(RcompTarget));
|
||||
}
|
||||
|
||||
int is_dual_channel(const int spd_index)
|
||||
{
|
||||
/* Per Makefile.inc, dual channel indices 1,3,5 */
|
||||
return (spd_index & 0x1);
|
||||
}
|
||||
Loading…
Reference in New Issue