armv7/exynos/snow: new cache maintenance API
This adds a new API for cache maintenance operations. The idea is to be more explicit about operations that are going on so it's easier to manage branch predictor, cache, and TLB cleans and invalidations. Also, this adds some operations that were missing but required early on, such as branch predictor invalidation. Instruction and sync barriers were wrong earlier as well since the imported API assumed we compield with -march=armv5 (which we don't) and was missing wrappers for the native ARMv7 ISB/DSB/DMB instructions. For now, this is a start and it gives us something we can easily use in libpayload for doing things like cleaning and invalidating dcache when doing DMA transfers. TODO: - Set cache policy explicitly before re-enabling. Right now it's left at default. - Finish deprecating old cache maintenance API. - We do an extra icache/dcache flush when going from bootblock to romstage. Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2729 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks
Ronald G. Minnich
parent
f7c6d489ae
commit
bba8090421
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@ -20,6 +20,7 @@
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*/
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#include <bootblock_common.h>
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#include <arch/cache.h>
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#include <arch/hlt.h>
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#include <arch/stages.h>
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#include <cbfs.h>
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@ -27,6 +28,58 @@
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#include "stages.c"
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static void armv7_invalidate_caches(void)
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{
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uint32_t clidr;
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int level;
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/* Invalidate branch predictor */
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bpiall();
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/* Iterate thru each cache identified in CLIDR and invalidate */
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clidr = read_clidr();
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for (level = 0; level < 7; level++) {
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unsigned int ctype = (clidr >> (level * 3)) & 0x7;
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uint32_t csselr;
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switch(ctype) {
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case 0x0:
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/* no cache */
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break;
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case 0x1:
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/* icache only */
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csselr = (level << 1) | 1;
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write_csselr(csselr);
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icache_invalidate_all();
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break;
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case 0x2:
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case 0x4:
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/* dcache only or unified cache */
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dcache_invalidate_all();
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break;
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case 0x3:
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/* separate icache and dcache */
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csselr = (level << 1) | 1;
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write_csselr(csselr);
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icache_invalidate_all();
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csselr = level < 1;
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write_csselr(csselr);
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dcache_invalidate_all();
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break;
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default:
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/* reserved */
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break;
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}
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}
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/* Invalidate TLB */
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/* FIXME: ARMv7 Architecture Ref. Manual claims that the distinction
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* instruction vs. data TLBs is deprecated in ARMv7. But that doesn't
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* really seem true for Cortex-A15? */
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tlb_invalidate_all();
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}
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static int boot_cpu(void)
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{
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/*
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@ -41,6 +94,24 @@ void main(void)
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{
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const char *stage_name = "fallback/romstage";
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void *entry;
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uint32_t sctlr;
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/* Globally disable MMU, caches, and branch prediction (these should
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* be disabled by default on reset) */
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sctlr = read_sctlr();
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sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
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write_sctlr(sctlr);
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armv7_invalidate_caches();
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/*
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* Re-enable caches and branch prediction. MMU will be set up later.
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* Note: If booting from USB, we need to disable branch prediction
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* before copying from USB into RAM (FIXME: why?)
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*/
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sctlr = read_sctlr();
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sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I;
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write_sctlr(sctlr);
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if (boot_cpu()) {
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bootblock_cpu_init();
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@ -0,0 +1,231 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef ARMV7_CACHE_H
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#define ARMV7_CACHE_H
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/* SCTLR bits */
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#define SCTLR_M (1 << 0) /* MMU enable */
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#define SCTLR_A (1 << 1) /* Alignment check enable */
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#define SCTLR_C (1 << 2) /* Data/unified cache enable */
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/* Bits 4:3 are reserved */
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#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */
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/* Bit 6 is reserved */
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#define SCTLR_B (1 << 7) /* Endianness */
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/* Bits 9:8 */
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#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
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#define SCTLR_Z (1 << 11) /* Branch prediction enable */
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#define SCTLR_I (1 << 12) /* Instruction cache enable */
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#define SCTLR_V (1 << 13) /* Low/high exception vectors */
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#define SCTLR_RR (1 << 14) /* Round Robin select */
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/* Bits 16:15 are reserved */
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#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
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/* Bit 18 is reserved */
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/* Bits 20:19 reserved virtualization not supported */
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#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
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#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission
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implies PL1 XN */
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#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */
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#define SCTLR_U (1 << 22) /* Unaligned access behavior */
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#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */
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#define SCTLR_EE (1 << 25) /* Exception endianness */
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/* Bit 26 is reserved */
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#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */
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#define SCTLR_TRE (1 << 28) /* TEX remap enable */
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#define SCTLR_AFE (1 << 29) /* Access flag enable */
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#define SCTLR_TE (1 << 30) /* Thumb exception enable */
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/* Bit 31 is reserved */
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/*
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* Sync primitives
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*/
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/* data memory barrier */
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static inline void dmb(void)
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{
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asm volatile ("dmb" : : : "memory");
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}
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/* data sync barrier */
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static inline void dsb(void)
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{
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asm volatile ("dsb" : : : "memory");
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}
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/* instruction sync barrier */
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static inline void isb(void)
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{
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asm volatile ("isb" : : : "memory");
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}
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/*
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* Low-level TLB maintenance operations
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*/
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/* invalidate entire data TLB */
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static inline void dtlbiall(void)
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{
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asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
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}
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/* invalidate entire instruction TLB */
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static inline void itlbiall(void)
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{
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asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
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}
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/* invalidate entire unified TLB */
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static inline void tlbiall(void)
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{
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asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
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}
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/*
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* Low-level cache maintenance operations
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*/
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/* branch predictor invalidate all */
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static inline void bpiall(void)
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{
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asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
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}
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/* data cache clean and invalidate by MVA to PoC */
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static inline void dccimvac(unsigned long mva)
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{
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asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
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}
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/* data cache invalidate by set/way */
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static inline void dccisw(uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
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}
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/* data cache invalidate by set/way */
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static inline void dcisw(uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val));
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}
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/* data cache clean by MVA to PoC */
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static inline void dccmvac(unsigned long mva)
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{
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asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva));
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}
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/* data cache invalidate by MVA to PoC */
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static inline void dcimvac(unsigned long mva)
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{
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asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
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}
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/* instruction cache invalidate all by PoU */
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static inline void iciallu(void)
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{
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
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}
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/*
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* Cache co-processor (CP15) access functions
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*/
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/* read cache level ID register (CLIDR) */
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static inline uint32_t read_clidr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val));
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return val;
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}
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/* read cache size ID register register (CCSIDR) */
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static inline uint32_t read_ccsidr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
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return val;
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}
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/* read cache size selection register (CSSELR) */
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static inline uint32_t read_csselr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val));
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return val;
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}
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/* write to cache size selection register (CSSELR) */
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static inline void write_csselr(uint32_t val)
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{
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/*
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* Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
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* Bit 0 - 0 = data or unified cache, 1 = instruction cache
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*/
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asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val));
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isb(); /* ISB to sync the change to CCSIDR */
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}
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/* read system control register (SCTLR) */
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static inline unsigned int read_sctlr(void)
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{
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unsigned int val;
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asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "cc");
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return val;
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}
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/* write system control register (SCTLR) */
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static inline void write_sctlr(unsigned int val)
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{
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asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc");
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isb();
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}
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/*
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* Cache maintenance API
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*/
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/* invalidate all TLBs */
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void tlb_invalidate_all(void);
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/* clean and invalidate entire dcache on current level (given by CCSELR) */
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void dcache_clean_invalidate_all(void);
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/* invalidate entire dcache on current level (given by CCSELR) */
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void dcache_invalidate_all(void);
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/* invalidate and clean dcache by machine virtual address to PoC */
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void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
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/* invalidate entire icache on current level (given by CSSELR) */
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void icache_invalidate_all(void);
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/* MMU setup by machine virtual address */
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void mmu_setup_by_mva(unsigned long start, unsigned long size);
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#endif /* ARMV7_CACHE_H */
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@ -21,6 +21,7 @@
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#define __ASM_ARM_IO_H
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#include <types.h>
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#include <arch/cache.h> /* for dmb() */
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#include <arch/byteorder.h>
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static inline void sync(void)
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@ -96,7 +97,7 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
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* TODO: The kernel offers some more advanced versions of barriers, it might
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* have some advantages to use them instead of the simple one here.
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*/
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#define dmb() __asm__ __volatile__ ("" : : : "memory")
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//#define dmb() __asm__ __volatile__ ("" : : : "memory")
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#define __iormb() dmb()
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#define __iowmb() dmb()
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@ -1,56 +0,0 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef _ASM_CACHE_H
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#define _ASM_CACHE_H
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/*
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* Invalidate L2 Cache using co-proc instruction
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*/
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static inline void invalidate_l2_cache(void)
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{
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unsigned int val=0;
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asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
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: : "r" (val) : "cc");
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isb();
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}
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void l2_cache_enable(void);
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void l2_cache_disable(void);
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/*
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* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
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* use that value for aligning DMA buffers unless the board config has specified
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* an alternate cache line size.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 64
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#endif
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inline void dram_bank_mmu_setup(unsigned long start, unsigned long size);
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#endif /* _ASM_CACHE_H */
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@ -43,13 +43,15 @@
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*/
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#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
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#define isb() __asm__ __volatile__ ("" : : : "memory")
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/* FIXME: conflicts with new implementation in cache.c */
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//#define isb() __asm__ __volatile__ ("" : : : "memory")
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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#define arch_align_stack(x) (x)
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#ifndef __ASSEMBLER__
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#include <arch/cache.h> /* for isb() */
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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|
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@ -97,6 +99,8 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop);
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void mmu_setup(unsigned long start, unsigned long size);
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void v7_inval_tlb(void);
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void arm_init_before_mmu(void);
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/*
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|
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@ -1,8 +1,12 @@
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#FIXME: cache_v7 and cache-cp15 will go away eventually
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bootblock-y += syslib.c
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bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c
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bootblock-y += cache.c
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bootblock-y += cache_v7.c
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bootblock-y += cache-cp15.c
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romstage-y += cache.c
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romstage-y += cache_v7.c
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romstage-y += cache-cp15.c
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romstage-y += div0.c
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@ -14,7 +18,9 @@ ramstage-y += div0.c
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#ramstage-y += memcpy.S
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#ramstage-y += memset.S
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ramstage-y += syslib.c
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ramstage-y += cache.c
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ramstage-y += cache_v7.c
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ramstage-y += cache-cp15.c
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#FIXME(dhendrix): should this be a config option?
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romstage-y += eabi_compat.c
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||||
|
|
|
|||
|
|
@ -123,8 +123,7 @@ inline void mmu_setup(unsigned long start, unsigned long size_mb)
|
|||
int i;
|
||||
u32 reg;
|
||||
|
||||
arm_init_before_mmu();
|
||||
|
||||
// arm_init_before_mmu();
|
||||
/* Set up an identity-mapping for all 4GB, rw for everyone */
|
||||
for (i = 0; i < 4096; i++)
|
||||
set_section_dcache(i, DCACHE_OFF);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2013 Google Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* cache.c: Low-level cache operations for ARMv7
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#include <arch/cache.h>
|
||||
|
||||
#define bitmask(high, low) ((1UL << (high)) + \
|
||||
((1UL << (high)) - 1) - ((1UL << (low)) - 1))
|
||||
|
||||
/* Basic log2() implementation. Note: log2(0) is 0 for our purposes. */
|
||||
/* FIXME: src/include/lib.h is difficult to work with due to romcc */
|
||||
static unsigned long log2(unsigned long u)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
while (u >>= 1)
|
||||
i++;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
void tlb_invalidate_all(void)
|
||||
{
|
||||
/*
|
||||
* FIXME: ARMv7 Architecture Ref. Manual claims that the distinction
|
||||
* instruction vs. data TLBs is deprecated in ARMv7. But that doesn't
|
||||
* really seem true for Cortex-A15?
|
||||
*/
|
||||
tlbiall();
|
||||
dtlbiall();
|
||||
itlbiall();
|
||||
isb();
|
||||
dsb();
|
||||
}
|
||||
|
||||
void icache_invalidate_all(void)
|
||||
{
|
||||
/* icache can be entirely invalidated with one operation.
|
||||
* Note: If branch predictors are architecturally-visible, ICIALLU
|
||||
* also performs a BPIALL operation (B2-1283 in arch manual)
|
||||
*/
|
||||
iciallu();
|
||||
isb();
|
||||
}
|
||||
|
||||
enum dcache_op {
|
||||
OP_DCCISW,
|
||||
OP_DCISW
|
||||
};
|
||||
|
||||
/* do a dcache operation on entire cache by set/way */
|
||||
static void dcache_op_set_way(enum dcache_op op)
|
||||
{
|
||||
uint32_t ccsidr;
|
||||
unsigned int associativity, num_sets, linesize_bytes;
|
||||
unsigned int set, way;
|
||||
unsigned int level;
|
||||
|
||||
level = (read_csselr() >> 1) & 0x7;
|
||||
|
||||
/*
|
||||
* dcache must be invalidated by set/way for portability since virtual
|
||||
* memory mapping is system-defined. The number of sets and
|
||||
* associativity is given by CCSIDR. We'll use DCISW to invalidate the
|
||||
* dcache.
|
||||
*/
|
||||
ccsidr = read_ccsidr();
|
||||
|
||||
/* FIXME: rounding up required here? */
|
||||
num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1;
|
||||
associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1;
|
||||
/* FIXME: do we need to use CTR.DminLine here? */
|
||||
linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4;
|
||||
|
||||
/*
|
||||
* Set/way operations require an interesting bit packing. See section
|
||||
* B4-35 in the ARMv7 Architecture Reference Manual:
|
||||
*
|
||||
* A: Log2(associativity)
|
||||
* B: L+S
|
||||
* L: Log2(linesize)
|
||||
* S: Log2(num_sets)
|
||||
*
|
||||
* The bits are packed as follows:
|
||||
* 31 31-A B B-1 L L-1 4 3 1 0
|
||||
* |---|-------------|--------|-------|-----|-|
|
||||
* |Way| zeros | Set | zeros |level|0|
|
||||
* |---|-------------|--------|-------|-----|-|
|
||||
*/
|
||||
for (way = 0; way < associativity; way++) {
|
||||
for (set = 0; set < num_sets; set++) {
|
||||
uint32_t val = 0;
|
||||
val |= way << (32 - log2(associativity));
|
||||
val |= set << log2(linesize_bytes);
|
||||
val |= level << 1;
|
||||
switch(op) {
|
||||
case OP_DCCISW:
|
||||
dccisw(val);
|
||||
break;
|
||||
case OP_DCISW:
|
||||
dcisw(val);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
dsb();
|
||||
}
|
||||
|
||||
void dcache_clean_invalidate_all(void)
|
||||
{
|
||||
dcache_op_set_way(OP_DCCISW);
|
||||
}
|
||||
|
||||
void dcache_invalidate_all(void)
|
||||
{
|
||||
dcache_op_set_way(OP_DCISW);
|
||||
}
|
||||
|
||||
static unsigned int line_bytes(void)
|
||||
{
|
||||
uint32_t ccsidr;
|
||||
unsigned int size;
|
||||
|
||||
ccsidr = read_ccsidr();
|
||||
/* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */
|
||||
size = 1 << ((ccsidr & 0x7) + 2); /* words per line */
|
||||
size *= sizeof(unsigned int); /* bytes per line */
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
|
||||
{
|
||||
unsigned long line, i;
|
||||
|
||||
line = line_bytes();
|
||||
for (i = addr & ~(line - 1); i < addr + len - 1; i += line)
|
||||
dccimvac(addr);
|
||||
}
|
||||
|
||||
/* FIXME: wrapper around imported mmu_setup() for now */
|
||||
extern void mmu_setup(unsigned long start, unsigned long size);
|
||||
void mmu_setup_by_mva(unsigned long start, unsigned long size)
|
||||
{
|
||||
mmu_setup(start, size);
|
||||
}
|
||||
|
|
@ -226,7 +226,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
|
|||
}
|
||||
|
||||
/* Invalidate TLB */
|
||||
static void v7_inval_tlb(void)
|
||||
void v7_inval_tlb(void)
|
||||
{
|
||||
/* Invalidate entire unified TLB */
|
||||
asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
|
||||
#include <arch/stages.h>
|
||||
#include <arch/armv7/include/common.h>
|
||||
#include <arch/cache.h>
|
||||
|
||||
void stage_entry(void)
|
||||
{
|
||||
|
|
@ -50,10 +51,10 @@ void stage_exit(void *addr)
|
|||
/* make sure any code we installed is written to memory. Not all ARM have
|
||||
* unified caches.
|
||||
*/
|
||||
flush_dcache_all();
|
||||
dcache_clean_invalidate_all();
|
||||
/* Because most stages copy code to memory, it's a safe and hygienic thing
|
||||
* to flush the icache here.
|
||||
*/
|
||||
invalidate_icache_all();
|
||||
icache_invalidate_all();
|
||||
doit();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@ ramstage-y += power.c
|
|||
ramstage-y += soc.c
|
||||
ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
|
||||
ramstage-y += cpu.c
|
||||
ramstage-y += exynos_cache.c
|
||||
|
||||
#ramstage-$(CONFIG_SATA_AHCI) += sata.c
|
||||
|
||||
|
|
|
|||
|
|
@ -33,17 +33,6 @@ enum l2_cache_params {
|
|||
CACHE_DATA_RAM_LATENCY = (2<<0)
|
||||
};
|
||||
|
||||
|
||||
/* FIXME(dhendrix): maybe move this to a romstage-specific file? */
|
||||
#ifdef __PRE_RAM__
|
||||
void enable_caches(void)
|
||||
{
|
||||
/* Enable D-cache. I-cache is already enabled in start.S */
|
||||
/* can't use it anyway -- it has dependencies we have to fix. */
|
||||
//dcache_enable();
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set L2 cache parameters
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -18,12 +18,12 @@
|
|||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <system.h>
|
||||
|
||||
#include <cache.h>
|
||||
#include <armv7.h>
|
||||
#include <cbfs.h>
|
||||
#include <common.h>
|
||||
|
||||
#include <arch/cache.h>
|
||||
#include <arch/gpio.h>
|
||||
#include <cpu/samsung/exynos5250/clk.h>
|
||||
#include <cpu/samsung/exynos5250/dmc.h>
|
||||
|
|
@ -52,20 +52,6 @@ static int board_wakeup_permitted(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set/clear program flow prediction and return the previous state.
|
||||
*/
|
||||
static int config_branch_prediction(int set_cr_z)
|
||||
{
|
||||
unsigned int cr;
|
||||
|
||||
/* System Control Register: 11th bit Z Branch prediction enable */
|
||||
cr = get_cr();
|
||||
set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
|
||||
|
||||
return cr & CR_Z;
|
||||
}
|
||||
|
||||
static void initialize_s5p_mshc(void)
|
||||
{
|
||||
/* MMC0: Fixed, 8 bit mode, connected with GPIO. */
|
||||
|
|
@ -95,10 +81,6 @@ void main(void)
|
|||
int ret;
|
||||
void *entry;
|
||||
|
||||
/* FIXME: if we boot from USB, we need to disable branch prediction
|
||||
* before copying from USB into RAM */
|
||||
config_branch_prediction(1);
|
||||
|
||||
clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
|
||||
|
||||
/* Clock must be initialized before console_init, otherwise you may need
|
||||
|
|
@ -108,7 +90,6 @@ void main(void)
|
|||
system_clock_init(mem, arm_ratios);
|
||||
|
||||
console_init();
|
||||
|
||||
/*
|
||||
* FIXME: Do necessary I2C init so low-level PMIC code doesn't need to.
|
||||
* Also, we should only call power_init() on cold boot.
|
||||
|
|
@ -132,7 +113,8 @@ void main(void)
|
|||
while(1);
|
||||
}
|
||||
|
||||
mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
|
||||
/* Set up MMU and caches */
|
||||
mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
|
||||
|
||||
initialize_s5p_mshc();
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue