intel fsp: remove CHIPSET_RESERVED_MEM_BYTES

FSP 1.1 platforms should be conforming to the spec. In order
to ensure following specification remove the crutch that allows
FSP to no conform.

BUG=chrome-os-partner:41961
BRANCH=None
TEST=Built.

Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a
Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285187
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/soc/intel/braswell/memmap.c

@@ -81,5 +81,5 @@ void *cbmem_top(void)
 	*/
 
 	smm_region((void **)&smm_base, &smm_size);
-	return (void *)(smm_base - CONFIG_CHIPSET_RESERVED_MEM_BYTES);
+	return (void *)smm_base;
 }

src/soc/intel/braswell/northcluster.c

@@ -52,8 +52,6 @@
  * +--------------------------+ SMMRRH, IRM0
  * |     TSEG                 |
  * +--------------------------+ SMMRRL
- * |     FSP Reserved Mem     |
- * +--------------------------+ SMMRRL - CONFIG_CHIPSET_RESERVED_MEM_BYTES
  * |     Usable DRAM          |
  * +--------------------------+ 0
  *

src/soc/intel/common/Kconfig

@@ -36,18 +36,6 @@ endif # CACHE_MRC_SETTINGS
 
 endif # HAVE_MRC
 
-config CHIPSET_RESERVED_MEM_BYTES
-	hex "Size in bytes of chipset reserved memory area"
-	default 0
-	help
-	  If insufficient documentation is available to determine the size of
-	  the chipset reserved memory area by walking the chipset registers,
-	  the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account
-	  for the missing pieces of memory.  The value specified in bytes is:
-
-	  value = TSEG base - top of low usable memory - (any sizes determined
-	  by reading chipset registers)
-
 config DISPLAY_MTRRS
 	bool "MTRRs: Display the MTRR settings"
 	default n

src/soc/intel/common/raminit.c

@@ -153,8 +153,6 @@ void raminit(struct romstage_params *params)
 #endif
 
 	/* Migrate CAR data */
-	printk(BIOS_DEBUG, "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n",
-		CONFIG_CHIPSET_RESERVED_MEM_BYTES);
 	printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
 	if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
 		cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
@@ -267,9 +265,6 @@ void raminit(struct romstage_params *params)
 			size_t delta_bytes = (unsigned int)smm_base
 				- cbmem_root->PhysicalStart
 				- cbmem_root->ResourceLength;
-			printk(BIOS_DEBUG,
-				"0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n",
-				CONFIG_CHIPSET_RESERVED_MEM_BYTES);
 			printk(BIOS_DEBUG,
 				"0x%08x: Chipset reserved bytes reported by FSP\n",
 				(unsigned int)delta_bytes);

src/soc/intel/skylake/memmap.c

@@ -96,6 +96,6 @@ void *cbmem_top(void)
 		top_of_ram = ALIGN_DOWN(top_of_ram, mmap_region_granluarity());
 	}
 
-	return (void *)(top_of_ram - CONFIG_CHIPSET_RESERVED_MEM_BYTES);
+	return (void *)top_of_ram;
 }
 

src/soc/intel/skylake/systemagent.c

@@ -351,15 +351,12 @@ static void mc_add_dram_resources(device_t dev)
 	base_k = 0xc0000 >> 10;
 	size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
 	size_k -= dpr_size >> 10;
-	size_k -= CONFIG_CHIPSET_RESERVED_MEM_BYTES >> 10;
 	ram_resource(dev, index++, base_k, size_k);
 
 	/* TSEG - DPR -> BGSM */
 	resource = new_resource(dev, index++);
 	resource->base = mc_values[TSEG_REG] - dpr_size;
 	resource->size = mc_values[BGSM_REG] - resource->base;
-	resource->base -= CONFIG_CHIPSET_RESERVED_MEM_BYTES;
-	resource->size += CONFIG_CHIPSET_RESERVED_MEM_BYTES;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 			  IORESOURCE_STORED | IORESOURCE_RESERVE |
 			  IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;