amdk8/amdfam10: Use CAR_GLOBAL for sysinfo

This gets rid of the somewhat unstructured placement of AMD's
sysinfo structure in CAR.
We used to carve out some CAR space using a Kconfig variable,
and then put sysinfo there manually (by "virtue" of pointer magic).

Now it's a variable with the CAR_GLOBAL qualifier, and build
system magic.

For this, the following steps were done (but must happen together
since the intermediates won't build):
- Add new CAR_GLOBAL sysinfo_car
- point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR
- remove DCACHE_RAM_GLOBAL_VAR_SIZE
  - from CAR setup (no need to reserve the space)
  - commented out code (that was commented out for years)
  - only copy sizeof(sysinfo) into RAM after ram init, where
    before it copied the whole GLOBAL_VAR area.
  - from Kconfig

Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>

src/cpu/Kconfig

@@ -15,10 +15,6 @@ config DCACHE_RAM_BASE
 config DCACHE_RAM_SIZE
 	hex
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x0
-
 # FIXME MAX_PHYSICAL_CPUS should move to AMD specific code, or better
 # yet be dropped completely.
 config MAX_PHYSICAL_CPUS

src/cpu/amd/car/cache_as_ram.inc

@@ -25,9 +25,6 @@
 #define CacheSize		CONFIG_DCACHE_RAM_SIZE
 #define CacheBase		(0xd0000 - CacheSize)
 
-/* Leave some space for global variable to pass to RAM stage. */
-#define GlobalVarSize		CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-
 /* For CAR with Fam10h. */
 #define CacheSizeAPStack	0x400 /* 1K */
 
@@ -348,7 +345,7 @@ fam10_end_part1:
 	rep	stosl
 
 	/* Set up the stack pointer. */
-	movl	$(CacheBase + CacheSize - GlobalVarSize), %eax
+	movl	$(CacheBase + CacheSize), %eax
 	movl	%eax, %esp
 
 	post_code(0xa3)
@@ -358,7 +355,7 @@ CAR_FAM10_ap:
 	/*
 	 * Need to set stack pointer for AP.
 	 * It will be from:
-	 *   CacheBase + (CacheSize - GlobalVarSize) / 2
+	 *   CacheBase + CacheSize / 2
 	 *   - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack
 	 * So need to get the NodeID and CoreID at first.
 	 * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need
@@ -392,7 +389,7 @@ roll_cfg:
 	/* Calculate stack pointer. */
 	movl	$CacheSizeAPStack, %eax
 	mull	%ebx
-	movl	$(CacheBase + (CacheSize - GlobalVarSize) / 2), %esp
+	movl	$(CacheBase + CacheSize / 2), %esp
 	subl	%eax, %esp
 
 	/* Retrive init detected. */

src/cpu/amd/car/post_cache_as_ram.c

@@ -164,12 +164,6 @@ static void post_cache_as_ram(void)
 
 	set_sysinfo_in_ram(1); // So other core0 could start to train mem
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
-//	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
-	// wait for ap memory to trained
-//	wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
-#endif
 	/*copy and execute coreboot_ram */
 	copy_and_run(0);
 	/* We will not return */

src/cpu/amd/model_10xxx/Kconfig

@@ -19,10 +19,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x0c000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x04000
-
 config UDELAY_IO
 	bool
 	default n

src/cpu/amd/model_fxx/model_fxx_init.c

@@ -32,7 +32,7 @@
 void cpus_ready_for_init(void)
 {
 #if CONFIG_MEM_TRAIN_SEQ == 1
-        struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox));
         // wait for ap memory to trained
         wait_all_core0_mem_trained(sysinfox);
 #endif

src/cpu/amd/socket_940/Kconfig

@@ -21,8 +21,4 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 endif # CPU_AMD_SOCKET_940

src/cpu/amd/socket_S1G1/Kconfig

@@ -31,8 +31,4 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 endif

src/mainboard/advansus/a785e-i/romstage.c

@@ -84,7 +84,7 @@ void soft_reset(void)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/amd/bimini_fam10/romstage.c

@@ -79,7 +79,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/amd/dbm690t/romstage.c

@@ -72,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */

src/mainboard/amd/mahogany/Kconfig

@@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0

src/mainboard/amd/mahogany/romstage.c

@@ -73,7 +73,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/amd/pistachio/Kconfig

@@ -31,10 +31,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0

src/mainboard/amd/pistachio/romstage.c

@@ -67,9 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo =
-	    (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
-				CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */

src/mainboard/amd/serengeti_cheetah/Kconfig

@@ -38,10 +38,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x8

src/mainboard/amd/serengeti_cheetah/ap_romstage.c

@@ -41,11 +41,8 @@ static inline unsigned get_nodes(void)
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE +
-			CONFIG_DCACHE_RAM_SIZE -
-			CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-	struct sys_info *sysinfox = ((CONFIG_RAMTOP) -
-			CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -110,7 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	};
 
-	struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
         int needs_reset;
         unsigned bsp_apicid = 0;
 #if CONFIG_SET_FIDVID

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -190,7 +190,7 @@ static const u8 spd_addr[] = {
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	u32 bsp_apicid = 0, val;
 	msr_t msr;
 

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/asrock/939a785gmh/Kconfig

@@ -35,10 +35,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0

src/mainboard/asrock/939a785gmh/romstage.c

@@ -139,7 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */

src/mainboard/asus/a8v-e_deluxe/Kconfig

@@ -31,10 +31,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x1000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/asus/a8v-e_deluxe/romstage.c

@@ -153,8 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	sio_init();
 	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/a8v-e_se/Kconfig

@@ -31,10 +31,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x1000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/asus/a8v-e_se/romstage.c

@@ -153,8 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	sio_init();
 	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/k8v-x/Kconfig

@@ -30,10 +30,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x1000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/asus/k8v-x/romstage.c

@@ -124,8 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	sio_init();
 	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/m2n-e/Kconfig

@@ -52,10 +52,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/asus/m2n-e/romstage.c

@@ -98,8 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM1, DIMM3, 0, 0,	/* Channel B (DIMM_B1, DIMM_B2) */
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 

src/mainboard/asus/m2v-mx_se/Kconfig

@@ -50,10 +50,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -132,8 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
-	struct sys_info *sysinfo =
-	    (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog();

src/mainboard/asus/m2v/Kconfig

@@ -35,10 +35,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x1000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/asus/m2v/romstage.c

@@ -230,8 +230,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
-	struct sys_info *sysinfo =
-	    (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	it8712f_24mhz_clkin();
 	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/m4a78-em/romstage.c

@@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/asus/m4a785-m/romstage.c

@@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/asus/m5a88-v/romstage.c

@@ -85,7 +85,7 @@ void soft_reset(void)
 #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/avalue/eax-785e/romstage.c

@@ -85,7 +85,7 @@ void soft_reset(void)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/broadcom/blast/Kconfig

@@ -29,10 +29,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x01000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x0
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0

src/mainboard/gigabyte/ga_2761gxdk/Kconfig

@@ -32,10 +32,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c

@@ -62,8 +62,8 @@
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -118,8 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
-		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = &sysinfo_car;
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
 

src/mainboard/gigabyte/m57sli/Kconfig

@@ -36,10 +36,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/gigabyte/m57sli/ap_romstage.c

@@ -60,8 +60,8 @@
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 

src/mainboard/gigabyte/m57sli/romstage.c

@@ -110,8 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = &sysinfo_car;
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
 	uint8_t tmp = 0;

src/mainboard/gigabyte/ma785gm/romstage.c

@@ -72,7 +72,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -72,7 +72,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/hp/dl145_g1/romstage.c

@@ -101,8 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		RC1|DIMM1, RC1|DIMM3, 0, 0,
 #endif
 	};
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;

src/mainboard/hp/dl145_g3/Kconfig

@@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x04000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x8

src/mainboard/hp/dl145_g3/romstage.c

@@ -134,8 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	int needs_reset;
 	unsigned bsp_apicid = 0;
 

src/mainboard/hp/dl165_g6_fam10/Kconfig

@@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x0c000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x04000
-
 config APIC_ID_OFFSET
 	hex
 	default 0

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -101,7 +101,7 @@ static const u8 spd_addr[] = {
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo =  (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	u32 bsp_apicid = 0, val;
 	msr_t msr;
 

src/mainboard/ibm/e325/Kconfig

@@ -28,10 +28,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x1000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x0
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0

src/mainboard/ibm/e326/Kconfig

@@ -28,10 +28,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x1000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x0
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -78,7 +78,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/iwill/dk8_htx/romstage.c

@@ -82,8 +82,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
         int needs_reset;
         unsigned bsp_apicid = 0;
 

src/mainboard/iwill/dk8s2/romstage.c

@@ -83,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                         DIMM5, DIMM7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
         int needs_reset;
         unsigned bsp_apicid = 0;
 

src/mainboard/iwill/dk8x/romstage.c

@@ -83,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
         int needs_reset;
         unsigned bsp_apicid = 0;
 

src/mainboard/jetway/pa78vm5/romstage.c

@@ -83,7 +83,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0, val;
 	msr_t msr;

src/mainboard/kontron/kt690/romstage.c

@@ -75,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */

src/mainboard/msi/ms7260/Kconfig

@@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/msi/ms7260/ap_romstage.c

@@ -49,10 +49,8 @@
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
-				    CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */
-	struct sys_info *sysinfox = ((CONFIG_RAMTOP) -
-				     CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */
+	struct sys_info *sysinfo = &sysinfo_car; /* in CACHE */
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); /* in RAM */
 	struct node_core_id id;
 
 	id = get_node_core_id_x();

src/mainboard/msi/ms7260/romstage.c

@@ -112,8 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 

src/mainboard/msi/ms9185/Kconfig

@@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x04000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x8

src/mainboard/msi/ms9185/romstage.c

@@ -103,8 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                        RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
        };
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
-		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
         int needs_reset;
         unsigned bsp_apicid = 0;

src/mainboard/msi/ms9282/Kconfig

@@ -32,10 +32,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x04000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/msi/ms9282/romstage.c

@@ -128,8 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	unsigned bsp_apicid = 0;
         int needs_reset;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
         if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */

src/mainboard/msi/ms9652_fam10/Kconfig

@@ -35,10 +35,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x0c000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x04000
-
 # Define to 0 because the IRQ slot count is
 # determined dynamically for this board.
 config IRQ_SLOT_COUNT

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -107,7 +107,7 @@ static const u8 spd_addr[] = {
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	u32 bsp_apicid = 0, val, wants_reset;
 	u8 reg;
 	msr_t msr;

src/mainboard/nvidia/l1_2pvv/Kconfig

@@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/nvidia/l1_2pvv/ap_romstage.c

@@ -58,8 +58,8 @@
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -111,8 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 

src/mainboard/siemens/sitemp_g1p1/romstage.c

@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */

src/mainboard/supermicro/h8dme/Kconfig

@@ -36,10 +36,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/supermicro/h8dme/ap_romstage.c

@@ -65,8 +65,8 @@ static inline unsigned get_nodes(void)
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 

src/mainboard/supermicro/h8dme/romstage.c

@@ -178,8 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		RC1 | DIMM5, RC1 | DIMM7,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 

src/mainboard/supermicro/h8dmr/Kconfig

@@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/supermicro/h8dmr/ap_romstage.c

@@ -65,8 +65,8 @@ static inline unsigned get_nodes(void)
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 

src/mainboard/supermicro/h8dmr/romstage.c

@@ -107,8 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = &sysinfo_car;
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
 

src/mainboard/supermicro/h8dmr_fam10/Kconfig

@@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x0c000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x04000
-
 config RAMBASE
 	hex
 	default 0x200000

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -109,8 +109,7 @@ static const u8 spd_addr[] = {
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
-		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	u32 bsp_apicid = 0, val, wants_reset;
 	msr_t msr;
 

src/mainboard/supermicro/h8qme_fam10/Kconfig

@@ -32,10 +32,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x0c000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x04000
-
 config RAMBASE
 	hex
 	default 0x200000

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -160,8 +160,7 @@ static void write_GPIO(void)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	u32 bsp_apicid = 0, val, wants_reset;
 	msr_t msr;
 

src/mainboard/supermicro/h8scm_fam10/romstage.c

@@ -86,7 +86,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {
 				RC00, 0x52,  0x53,  0, 0, 0x50,  0x51,  0, 0,
 				//RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0,

src/mainboard/technexion/tim5690/romstage.c

@@ -74,7 +74,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */

src/mainboard/technexion/tim8690/romstage.c

@@ -72,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */

src/mainboard/tyan/s2912/Kconfig

@@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10

src/mainboard/tyan/s2912/ap_romstage.c

@@ -56,8 +56,8 @@
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 

src/mainboard/tyan/s2912/romstage.c

@@ -112,8 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 

src/mainboard/tyan/s2912_fam10/Kconfig

@@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x0c000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x04000
-
 config APIC_ID_OFFSET
 	hex
 	default 0

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -113,7 +113,7 @@ static const u8 spd_addr[] = {
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 
 	u32 bsp_apicid = 0, val, wants_reset;
 	msr_t msr;

src/northbridge/amd/amdfam10/acpi.c

@@ -134,7 +134,7 @@ unsigned long acpi_fill_slit(unsigned long current)
 	/* fill the first 8 byte with that num */
 	/* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
 
-	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox));
 	u8 *ln = sysinfox->ln;
 
 

src/northbridge/amd/amdfam10/amdfam10.h

@@ -1098,6 +1098,10 @@ struct sys_info {
 
 } __attribute__((packed));
 
+#ifdef __PRE_RAM__
+extern struct sys_info sysinfo_car;
+#endif
+
 #ifndef __PRE_RAM__
 device_t get_node_pci(u32 nodeid, u32 fn);
 #endif

src/northbridge/amd/amdfam10/northbridge.c

@@ -773,7 +773,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 	u32 hole_sizek;
 
 	u32 one_DCT;
-	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 	struct mem_info *meminfo;
 	meminfo = &sysinfox->meminfo[node_id];
 
@@ -1056,7 +1056,7 @@ static void amdfam10_domain_set_resources(device_t dev)
 				#if !CONFIG_AMDMCT
 				#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 				if(reset_memhole) {
-					struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+					struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 					struct mem_info *meminfo;
 					meminfo = &sysinfox->meminfo[i];
 					sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes);

src/northbridge/amd/amdfam10/raminit_amdmct.c

@@ -120,6 +120,9 @@ static  void print_t(const char *strval)
 
 #endif	/* DDR2 */
 
+#include <cpu/x86/car.h>
+struct sys_info sysinfo_car CAR_GLOBAL;
+
 int mctRead_SPD(u32 smaddr, u32 reg)
 {
 	return spd_read_byte(smaddr, reg);
@@ -128,7 +131,7 @@ int mctRead_SPD(u32 smaddr, u32 reg)
 
 void mctSMBhub_Init(u32 node)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
 	activate_spd_rom(ctrl);
 }
@@ -137,7 +140,7 @@ void mctSMBhub_Init(u32 node)
 void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
 {
 	int j;
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
 
 	for(j=0;j<DIMM_SOCKETS;j++) {

src/northbridge/amd/amdk8/f.h

@@ -518,6 +518,10 @@ struct sys_info {
 	uint32_t sbbusn;
 } __attribute__((packed));
 
+#ifdef __PRE_RAM__
+extern struct sys_info sysinfo_car;
+#endif
+
 #include <reset.h>
 
 #if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \

src/northbridge/amd/amdk8/pre_f.h

@@ -262,4 +262,8 @@ struct sys_info {
 	uint32_t sbbusn;
 } __attribute__((packed));
 
+#ifdef __PRE_RAM__
+extern struct sys_info sysinfo_car;
+#endif
+
 #endif /* AMDK8_PRE_F_H */

src/northbridge/amd/amdk8/raminit.c

@@ -14,6 +14,9 @@
 #include "option_table.h"
 #endif
 
+#include <cpu/x86/car.h>
+struct sys_info sysinfo_car CAR_GLOBAL;
+
 #if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
 # error "CONFIG_RAMTOP must be a power of 2"
 #endif

src/northbridge/amd/amdk8/raminit_f.c

@@ -39,6 +39,9 @@
 #endif
 
 
+#include <cpu/x86/car.h>
+struct sys_info sysinfo_car CAR_GLOBAL;
+
 #if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
 # error "CONFIG_RAMTOP must be a power of 2"
 #endif