binaryPI: Drop CONFIG_CBB and CONFIG_CDB
Static values, copy paste from multi-node fam15 code. Add header that shall have declarations of functions common to different families factored out. Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -23,14 +23,6 @@ config CPU_ADDR_BITS
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int
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default 48
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config CBB
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hex
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default 0x0
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config CDB
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hex
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default 0x18
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config XIP_ROM_SIZE
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hex
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default 0x100000
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@ -23,14 +23,6 @@ config CPU_ADDR_BITS
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int
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default 48
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config CBB
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hex
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default 0x0
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config CDB
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hex
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default 0x18
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config XIP_ROM_SIZE
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hex
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default 0x100000
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@ -23,14 +23,6 @@ config CPU_ADDR_BITS
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int
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default 40
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config CBB
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hex
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default 0x0
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config CDB
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hex
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default 0x18
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config XIP_ROM_SIZE
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hex
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default 0x100000
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@ -34,6 +34,7 @@
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#include <cpu/amd/mtrr.h>
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#include <arch/acpigen.h>
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#include <assert.h>
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#include <northbridge/amd/pi/nb_common.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
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#include <northbridge/amd/pi/agesawrapper.h>
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@ -102,7 +103,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
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static struct device *get_node_pci(u32 nodeid, u32 fn)
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{
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return pcidev_on_root(CONFIG_CDB + nodeid, fn);
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return pcidev_on_root(DEV_CDB + nodeid, fn);
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}
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static void get_fx_devs(void)
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@ -145,7 +146,7 @@ static void f1_write_config32(unsigned reg, u32 value)
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static u32 amdfam15_nodeid(struct device *dev)
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{
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return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
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return (dev->path.pci.devfn >> 3) - DEV_CDB;
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}
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static void set_vga_enable_reg(u32 nodeid, u32 linkn)
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@ -853,9 +854,9 @@ static void cpu_bus_scan(struct device *dev)
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printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules);
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printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics));
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dev_mc = pcidev_on_root(CONFIG_CDB, 0);
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dev_mc = pcidev_on_root(DEV_CDB, 0);
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if (!dev_mc) {
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printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
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printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
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die("");
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}
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sysconf_init(dev_mc);
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@ -878,7 +879,7 @@ static void cpu_bus_scan(struct device *dev)
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unsigned devn;
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struct bus *pbus;
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devn = CONFIG_CDB + i;
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devn = DEV_CDB + i;
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pbus = dev_mc->bus;
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/* Find the cpu's pci device */
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@ -33,6 +33,7 @@
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <arch/acpigen.h>
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#include <northbridge/amd/pi/nb_common.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
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#include <northbridge/amd/pi/agesawrapper.h>
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@ -101,7 +102,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
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static struct device *get_node_pci(u32 nodeid, u32 fn)
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{
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return pcidev_on_root(CONFIG_CDB + nodeid, fn);
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return pcidev_on_root(DEV_CDB + nodeid, fn);
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}
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static void get_fx_devs(void)
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@ -144,7 +145,7 @@ static void f1_write_config32(unsigned reg, u32 value)
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static u32 amdfam15_nodeid(struct device *dev)
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{
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return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
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return (dev->path.pci.devfn >> 3) - DEV_CDB;
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}
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static void set_vga_enable_reg(u32 nodeid, u32 linkn)
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@ -843,9 +844,9 @@ static void cpu_bus_scan(struct device *dev)
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ioapic_count = (int)options->CfgPlatNumIoApics;
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ASSERT(ioapic_count > 0);
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dev_mc = pcidev_on_root(CONFIG_CDB, 0);
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dev_mc = pcidev_on_root(DEV_CDB, 0);
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if (!dev_mc) {
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printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
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printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
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die("");
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}
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sysconf_init(dev_mc);
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@ -868,7 +869,7 @@ static void cpu_bus_scan(struct device *dev)
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unsigned devn;
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struct bus *pbus;
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devn = CONFIG_CDB + i;
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devn = DEV_CDB + i;
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pbus = dev_mc->bus;
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/* Find the cpu's pci device */
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@ -35,6 +35,7 @@
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <arch/acpigen.h>
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#include <northbridge/amd/pi/nb_common.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
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#include <northbridge/amd/pi/agesawrapper.h>
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@ -103,7 +104,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
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static struct device *get_node_pci(u32 nodeid, u32 fn)
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{
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return pcidev_on_root(CONFIG_CDB + nodeid, fn);
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return pcidev_on_root(DEV_CDB + nodeid, fn);
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}
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static void get_fx_devs(void)
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@ -146,7 +147,7 @@ static void f1_write_config32(unsigned reg, u32 value)
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static u32 amdfam16_nodeid(struct device *dev)
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{
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return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
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return (dev->path.pci.devfn >> 3) - DEV_CDB;
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}
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static void set_vga_enable_reg(u32 nodeid, u32 linkn)
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@ -1089,9 +1090,9 @@ static void cpu_bus_scan(struct device *dev)
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printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules);
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printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics);
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dev_mc = pcidev_on_root(CONFIG_CDB, 0);
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dev_mc = pcidev_on_root(DEV_CDB, 0);
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if (!dev_mc) {
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printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
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printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
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die("");
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}
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sysconf_init(dev_mc);
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@ -1114,7 +1115,7 @@ static void cpu_bus_scan(struct device *dev)
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unsigned devn;
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struct bus *pbus;
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devn = CONFIG_CDB + i;
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devn = DEV_CDB + i;
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pbus = dev_mc->bus;
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/* Find the cpu's pci device */
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@ -0,0 +1,19 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __AMD_NB_COMMON_H__
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#define __AMD_NB_COMMON_H__
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#define DEV_CDB 0x18
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#endif
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