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binaryPI: Drop CONFIG_CBB and CONFIG_CDB 

Static values, copy paste from multi-node fam15 code.

Add header that shall have declarations of functions
common to different families factored out.

Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2019-01-10 05:41:23 +02:00
parent c27776dbaf
commit bbd237702a
7 changed files with 37 additions and 39 deletions
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8
src/cpu/amd/pi/00630F01/Kconfig
View File

@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int int
default 48 default 48
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE config XIP_ROM_SIZE
hex hex
default 0x100000 default 0x100000

8
src/cpu/amd/pi/00660F01/Kconfig
View File

@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int int
default 48 default 48
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE config XIP_ROM_SIZE
hex hex
default 0x100000 default 0x100000

8
src/cpu/amd/pi/00730F01/Kconfig
View File

@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int int
default 40 default 40
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE config XIP_ROM_SIZE
hex hex
default 0x100000 default 0x100000

11
src/northbridge/amd/pi/00630F01/northbridge.c
View File

@ -34,6 +34,7 @@
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
#include <assert.h> #include <assert.h>
#include <northbridge/amd/pi/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
@ -102,7 +103,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn) static struct device *get_node_pci(u32 nodeid, u32 fn)
{ {
return pcidev_on_root(CONFIG_CDB + nodeid, fn); return pcidev_on_root(DEV_CDB + nodeid, fn);
} }
static void get_fx_devs(void) static void get_fx_devs(void)
@ -145,7 +146,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam15_nodeid(struct device *dev) static u32 amdfam15_nodeid(struct device *dev)
{ {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB; return (dev->path.pci.devfn >> 3) - DEV_CDB;
} }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) static void set_vga_enable_reg(u32 nodeid, u32 linkn)
@ -853,9 +854,9 @@ static void cpu_bus_scan(struct device *dev)
printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules);
printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics)); printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics));
dev_mc = pcidev_on_root(CONFIG_CDB, 0); dev_mc = pcidev_on_root(DEV_CDB, 0);
if (!dev_mc) { if (!dev_mc) {
printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
die(""); die("");
} }
sysconf_init(dev_mc); sysconf_init(dev_mc);
@ -878,7 +879,7 @@ static void cpu_bus_scan(struct device *dev)
unsigned devn; unsigned devn;
struct bus *pbus; struct bus *pbus;
devn = CONFIG_CDB + i; devn = DEV_CDB + i;
pbus = dev_mc->bus; pbus = dev_mc->bus;
/* Find the cpu's pci device */ /* Find the cpu's pci device */

11
src/northbridge/amd/pi/00660F01/northbridge.c
View File

@ -33,6 +33,7 @@
#include <cpu/amd/msr.h> #include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
#include <northbridge/amd/pi/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
@ -101,7 +102,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn) static struct device *get_node_pci(u32 nodeid, u32 fn)
{ {
return pcidev_on_root(CONFIG_CDB + nodeid, fn); return pcidev_on_root(DEV_CDB + nodeid, fn);
} }
static void get_fx_devs(void) static void get_fx_devs(void)
@ -144,7 +145,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam15_nodeid(struct device *dev) static u32 amdfam15_nodeid(struct device *dev)
{ {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB; return (dev->path.pci.devfn >> 3) - DEV_CDB;
} }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) static void set_vga_enable_reg(u32 nodeid, u32 linkn)
@ -843,9 +844,9 @@ static void cpu_bus_scan(struct device *dev)
ioapic_count = (int)options->CfgPlatNumIoApics; ioapic_count = (int)options->CfgPlatNumIoApics;
ASSERT(ioapic_count > 0); ASSERT(ioapic_count > 0);
dev_mc = pcidev_on_root(CONFIG_CDB, 0); dev_mc = pcidev_on_root(DEV_CDB, 0);
if (!dev_mc) { if (!dev_mc) {
printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
die(""); die("");
} }
sysconf_init(dev_mc); sysconf_init(dev_mc);
@ -868,7 +869,7 @@ static void cpu_bus_scan(struct device *dev)
unsigned devn; unsigned devn;
struct bus *pbus; struct bus *pbus;
devn = CONFIG_CDB + i; devn = DEV_CDB + i;
pbus = dev_mc->bus; pbus = dev_mc->bus;
/* Find the cpu's pci device */ /* Find the cpu's pci device */

11
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -35,6 +35,7 @@
#include <cpu/amd/msr.h> #include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
#include <northbridge/amd/pi/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
@ -103,7 +104,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn) static struct device *get_node_pci(u32 nodeid, u32 fn)
{ {
return pcidev_on_root(CONFIG_CDB + nodeid, fn); return pcidev_on_root(DEV_CDB + nodeid, fn);
} }
static void get_fx_devs(void) static void get_fx_devs(void)
@ -146,7 +147,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam16_nodeid(struct device *dev) static u32 amdfam16_nodeid(struct device *dev)
{ {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB; return (dev->path.pci.devfn >> 3) - DEV_CDB;
} }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) static void set_vga_enable_reg(u32 nodeid, u32 linkn)
@ -1089,9 +1090,9 @@ static void cpu_bus_scan(struct device *dev)
printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules);
printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics); printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics);
dev_mc = pcidev_on_root(CONFIG_CDB, 0); dev_mc = pcidev_on_root(DEV_CDB, 0);
if (!dev_mc) { if (!dev_mc) {
printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
die(""); die("");
} }
sysconf_init(dev_mc); sysconf_init(dev_mc);
@ -1114,7 +1115,7 @@ static void cpu_bus_scan(struct device *dev)
unsigned devn; unsigned devn;
struct bus *pbus; struct bus *pbus;
devn = CONFIG_CDB + i; devn = DEV_CDB + i;
pbus = dev_mc->bus; pbus = dev_mc->bus;
/* Find the cpu's pci device */ /* Find the cpu's pci device */

19
src/northbridge/amd/pi/nb_common.h Normal file
View File

@ -0,0 +1,19 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __AMD_NB_COMMON_H__
#define __AMD_NB_COMMON_H__
#define DEV_CDB 0x18
#endif