soc/intel/braswell: convert to using common MP and SMM init
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I65beefec53a29b2861433bc42679f3fa571d5b6a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14593 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin
parent
8346b04445
commit
bbe4a7e944
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@ -33,40 +33,8 @@
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#include <soc/smm.h>
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#include <stdlib.h>
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static void smm_relocate(void);
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static void enable_smis(void);
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static void pre_smm_relocation(void);
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static struct mp_flight_record mp_steps[] = {
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MP_FR_BLOCK_APS(pre_smm_relocation, pre_smm_relocation),
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MP_FR_BLOCK_APS(smm_relocate, smm_relocate),
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MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
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/* Wait for APs to finish initialization before proceeding. */
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MP_FR_BLOCK_APS(NULL, enable_smis),
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};
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/* The APIC id space is sparse. Each id is separated by 2. */
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static int adjust_apic_id(int index, int apic_id)
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{
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return 2 * index;
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}
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/* Package level MSRs */
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const struct reg_script package_msr_script[] = {
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/* Set Package TDP to ~7W */
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REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa),
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REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0),
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REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702),
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REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b),
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REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0),
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REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305),
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REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d),
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REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27),
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REG_SCRIPT_END
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};
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/* Core level MSRs */
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const struct reg_script core_msr_script[] = {
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static const struct reg_script core_msr_script[] = {
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/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
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REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
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REG_MSR_RMW(MSR_POWER_MISC,
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@ -77,50 +45,6 @@ const struct reg_script core_msr_script[] = {
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REG_SCRIPT_END
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};
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void soc_init_cpus(device_t dev)
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{
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struct bus *cpu_bus = dev->link_list;
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const struct pattrs *pattrs = pattrs_get();
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struct mp_params mp_params;
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void *default_smm_area;
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uint32_t bsmrwac;
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printk(BIOS_SPEW, "%s/%s ( %s )\n",
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__FILE__, __func__, dev_name(dev));
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/* Set up MTRRs based on physical address size. */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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mp_params.num_cpus = pattrs->num_cpus,
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mp_params.parallel_microcode_load = 1,
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mp_params.adjust_apic_id = adjust_apic_id;
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mp_params.flight_plan = &mp_steps[0];
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mp_params.num_records = ARRAY_SIZE(mp_steps);
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mp_params.microcode_pointer = pattrs->microcode_patch;
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default_smm_area = backup_default_smm_area();
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/*
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* Configure the BUNIT to allow dirty cache line evictions in non-SMM
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* mode for the lines that were dirtied while in SMM mode. Otherwise
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* the writes would be silently dropped.
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*/
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bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
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iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
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/* Set package MSRs */
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reg_script_run(package_msr_script);
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/* Enable Turbo Mode on BSP and siblings of the BSP's building block. */
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enable_turbo();
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if (mp_init(cpu_bus, &mp_params))
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printk(BIOS_ERR, "MP initialization failure.\n");
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restore_default_smm_area(default_smm_area);
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}
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static void soc_core_init(device_t cpu)
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{
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printk(BIOS_SPEW, "%s/%s ( %s )\n",
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@ -161,7 +85,7 @@ static const struct cpu_driver driver __cpu_driver = {
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/*
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* SMM loading and initialization.
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* MP and SMM loading initialization.
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*/
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struct smm_relocation_attrs {
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@ -172,32 +96,107 @@ struct smm_relocation_attrs {
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static struct smm_relocation_attrs relo_attrs;
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static void adjust_apic_id_map(struct smm_loader_params *smm_params)
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{
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int i;
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struct smm_runtime *runtime = smm_params->runtime;
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/* Package level MSRs */
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static const struct reg_script package_msr_script[] = {
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/* Set Package TDP to ~7W */
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REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa),
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REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0),
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REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702),
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REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b),
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REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0),
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REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305),
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REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d),
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REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27),
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REG_SCRIPT_END
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};
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for (i = 0; i < CONFIG_MAX_CPUS; i++)
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runtime->apic_id_to_cpu[i] = mp_get_apic_id(i);
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static void pre_mp_init(void)
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{
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uint32_t bsmrwac;
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/* Set up MTRRs based on physical address size. */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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/*
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* Configure the BUNIT to allow dirty cache line evictions in non-SMM
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* mode for the lines that were dirtied while in SMM mode. Otherwise
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* the writes would be silently dropped.
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*/
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bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
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iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
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/* Set package MSRs */
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reg_script_run(package_msr_script);
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/* Enable Turbo Mode on BSP and siblings of the BSP's building block. */
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enable_turbo();
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}
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static void asmlinkage cpu_smm_do_relocation(void *arg)
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static int get_cpu_count(void)
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{
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const struct pattrs *pattrs = pattrs_get();
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return pattrs->num_cpus;
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}
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size)
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{
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void *smm_base;
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size_t smm_size;
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/* All range registers are aligned to 4KiB */
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const uint32_t rmask = ~((1 << 12) - 1);
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/* Initialize global tracking state. */
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smm_region(&smm_base, &smm_size);
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relo_attrs.smbase = (uint32_t)smm_base;
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relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
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relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
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relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
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*perm_smbase = relo_attrs.smbase;
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*perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE;
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*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
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}
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/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */
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static int adjust_apic_id(int index, int apic_id)
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{
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return 2 * index;
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}
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static void get_microcode_info(const void **microcode, int *parallel)
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{
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const struct pattrs *pattrs = pattrs_get();
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*microcode = pattrs->microcode_patch;
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*parallel = 1;
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}
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static void per_cpu_smm_trigger(void)
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{
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const struct pattrs *pattrs = pattrs_get();
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msr_t msr_value;
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/* Need to make sure that all cores have microcode loaded. */
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msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID);
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if (msr_value.hi == 0)
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intel_microcode_load_unlocked(pattrs->microcode_patch);
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/* Relocate SMM space. */
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smm_initiate_relocation();
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/* Load microcode after SMM relocation. */
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intel_microcode_load_unlocked(pattrs->microcode_patch);
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}
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static void relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase)
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{
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msr_t smrr;
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em64t100_smm_state_save_area_t *smm_state;
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const struct smm_module_params *p;
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const struct smm_runtime *runtime;
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int cpu;
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p = arg;
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runtime = p->runtime;
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cpu = p->cpu;
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if (cpu >= CONFIG_MAX_CPUS) {
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printk(BIOS_CRIT,
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"Invalid CPU number assigned in SMM stub: %d\n", cpu);
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return;
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}
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/* Set up SMRR. */
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smrr.lo = relo_attrs.smrr_base;
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@ -207,130 +206,30 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
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smrr.hi = 0;
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wrmsr(SMRR_PHYS_MASK, smrr);
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/*
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* The relocated handler runs with all CPUs concurrently. Therefore
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* stagger the entry points adjusting SMBASE downwards by save state
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* size * CPU num.
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*/
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smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase);
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smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size;
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printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase);
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smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
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smm_state->smbase = staggered_smbase;
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}
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static int install_relocation_handler(int num_cpus)
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = get_smm_info,
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.get_microcode_info = get_microcode_info,
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.adjust_cpu_apic_entry = adjust_apic_id,
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.pre_mp_smm_init = southcluster_smm_clear_state,
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.per_cpu_smm_trigger = per_cpu_smm_trigger,
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.relocation_handler = relocation_handler,
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.post_mp_init = southcluster_smm_enable_smi,
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};
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void soc_init_cpus(device_t dev)
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{
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const int save_state_size = sizeof(em64t100_smm_state_save_area_t);
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struct bus *cpu_bus = dev->link_list;
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = num_cpus,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = 1,
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.handler = (smm_handler_t)&cpu_smm_do_relocation,
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};
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printk(BIOS_SPEW, "%s/%s ( %s )\n",
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__FILE__, __func__, dev_name(dev));
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if (smm_setup_relocation_handler(&smm_params))
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return -1;
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adjust_apic_id_map(&smm_params);
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return 0;
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}
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static int install_permanent_handler(int num_cpus)
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{
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/*
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* There are num_cpus concurrent stacks and num_cpus concurrent save
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* state areas. Lastly, set the stack size to the save state size.
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*/
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int save_state_size = sizeof(em64t100_smm_state_save_area_t);
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = num_cpus,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = num_cpus,
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};
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void *smm_base;
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size_t smm_size;
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int tseg_size;
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printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
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relo_attrs.smbase);
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smm_region(&smm_base, &smm_size);
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tseg_size = smm_size - CONFIG_SMM_RESERVED_SIZE;
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if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params))
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return -1;
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adjust_apic_id_map(&smm_params);
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return 0;
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}
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static int smm_load_handlers(void)
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{
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/* All range registers are aligned to 4KiB */
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const uint32_t rmask = ~((1 << 12) - 1);
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const struct pattrs *pattrs = pattrs_get();
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void *smm_base;
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size_t smm_size;
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/* Initialize global tracking state. */
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smm_region(&smm_base, &smm_size);
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relo_attrs.smbase = (uint32_t)smm_base;
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relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
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relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
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relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
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/* Install handlers. */
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if (install_relocation_handler(pattrs->num_cpus) < 0) {
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printk(BIOS_ERR, "Unable to install SMM relocation handler.\n");
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return -1;
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if (mp_init_with_smm(cpu_bus, &mp_ops)) {
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printk(BIOS_ERR, "MP initialization failure.\n");
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}
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if (install_permanent_handler(pattrs->num_cpus) < 0) {
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printk(BIOS_ERR, "Unable to install SMM permanent handler.\n");
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return -1;
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}
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/* Ensure the SMM handlers hit DRAM before performing first SMI. */
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wbinvd();
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return 0;
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}
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static void pre_smm_relocation(void)
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{
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const struct pattrs *pattrs = pattrs_get();
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msr_t msr_value;
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/* Need to make sure that all cores have microcode loaded. */
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msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID);
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if (msr_value.hi == 0)
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intel_microcode_load_unlocked(pattrs->microcode_patch);
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}
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static void smm_relocate(void)
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{
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const struct pattrs *pattrs = pattrs_get();
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/* Load relocation and permanent handler. */
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if (boot_cpu()) {
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if (smm_load_handlers() < 0) {
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printk(BIOS_ERR, "Error loading SMM handlers.\n");
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return;
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}
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southcluster_smm_clear_state();
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}
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/* Relocate SMM space. */
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smm_initiate_relocation();
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/* Load microcode after SMM relocation. */
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intel_microcode_load_unlocked(pattrs->microcode_patch);
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}
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static void enable_smis(void)
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{
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southcluster_smm_enable_smi();
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}
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