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Documentation: Fix a few spelling issues 

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I47add663f3021170b840203ce229acf836b7a1c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Martin Roth 2022-05-28 12:32:02 -06:00 committed by Martin L Roth
parent 7b9d08e849
commit bbe876250f
3 changed files with 3 additions and 3 deletions
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2
Documentation/getting_started/architecture.md
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@ -3,7 +3,7 @@
## Overview ## Overview
![][architecture] ![][architecture]
[architecture]: comparision_coreboot_uefi.svg [architecture]: comparison_coreboot_uefi.svg
## Stages ## Stages
coreboot consists of multiple stages that are compiled as separate binaries and coreboot consists of multiple stages that are compiled as separate binaries and

2
Documentation/mainboard/acer/g43t-am3.md
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@ -134,7 +134,7 @@ SPI_ROM1 header while the board is off and disconnected from power. There
seems to be a diode that prevents the external programmer from powering the seems to be a diode that prevents the external programmer from powering the
whole board. whole board.
The signal assigment on the header is identical to the pinout of the flash The signal assignment on the header is identical to the pinout of the flash
chip. The pinout diagram below is valid when the PCI slots are on the left chip. The pinout diagram below is valid when the PCI slots are on the left
and the CPU is on the right. Note that HOLD# and WP# must be pulled high and the CPU is on the right. Note that HOLD# and WP# must be pulled high
(to VCC) to be able to flash the chip. (to VCC) to be able to flash the chip.

2
Documentation/northbridge/intel/sandybridge/nri_registers.md
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@ -1899,7 +1899,7 @@ Please handle with care!
+===========+==================================================================+ +===========+==================================================================+
| 0:7| PDWN_idle_counter, This defines the rank indle period in DCLK | | 0:7| PDWN_idle_counter, This defines the rank indle period in DCLK |
| | cycles that causes power-down entrance. The minimum value | | | cycles that causes power-down entrance. The minimum value |
| | should be greater then or equal to the worst roundtrip time | | | should be greater than or equal to the worst roundtrip time |
| | plus burst length. | | | plus burst length. |
+-----------+------------------------------------------------------------------+ +-----------+------------------------------------------------------------------+
| 8:10| PDWN_mode, selects the mode of power-down: | | 8:10| PDWN_mode, selects the mode of power-down: |