google/chell: Modify DqsMap
Modify Dqs Byte Swizzling for channel 0 to honor chell's memory routing BUG=chrome-os-partner:48986 BRANCH=glados TEST=verified on chell system Signed-off-by: Mike Hsieh <mike.m.hsieh@intel.com> Change-Id: Ic0485526bc1378e329c5eb0eeb57ff67a9501e86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b60241e63381974655f5df5afcd913e95c17682b Original-Change-Id: I641502e8d303fa59e0f668d581745379e1ef4853 Original-Reviewed-on: https://chromium-review.googlesource.com/321524 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -29,7 +29,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
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0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
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/* DQS CPU<>DRAM map */
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/* DQS CPU<>DRAM map */
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const u8 dqs_map[2][8] = {
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const u8 dqs_map[2][8] = {
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{ 0, 1, 3, 2, 4, 5, 6, 7 },
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{ 0, 3, 1, 2, 4, 5, 6, 7 },
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{ 1, 0, 4, 5, 2, 3, 6, 7 } };
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{ 1, 0, 4, 5, 2, 3, 6, 7 } };
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/* Rcomp resistor */
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/* Rcomp resistor */
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