nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash

CBFS could start from below 4MB, and should be cacheable for the
purpose of early microcode update and CBFS search for romstage file.

Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4626
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/cpu/intel/haswell/bootblock.c

@@ -54,8 +54,7 @@ static void enable_rom_caching(void)
 	msr_t msr;
 
 	disable_cache();
-	/* Why only top 4MiB ? */
+	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
-	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
 	enable_cache();
 
 	/* Enable Variable MTRRs */

src/cpu/intel/model_2065x/bootblock.c

@@ -53,7 +53,7 @@ static void enable_rom_caching(void)
 	msr_t msr;
 
 	disable_cache();
-	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
 	enable_cache();
 
 	/* Enable Variable MTRRs */

src/cpu/intel/model_206ax/bootblock.c

@@ -54,7 +54,7 @@ static void enable_rom_caching(void)
 	msr_t msr;
 
 	disable_cache();
-	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
 	enable_cache();
 
 	/* Enable Variable MTRRs */