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sb/amd/hudson/spi.c: Use C over CPP conditional 

Change-Id: Ie6e2420813e1b3e8885499b4739b1222aa1b46e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2022-03-23 22:41:05 +01:00 committed by Felix Held
parent f128adda88
commit bbf5de55ca
1 changed files with 9 additions and 9 deletions
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18
src/southbridge/amd/agesa/hudson/spi.c
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@ -97,15 +97,15 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
readoffby1 = bytesout ? 0 : 1;
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
spi_write(0x1E, 5);
spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */
spi_write(0x1E, 6);
spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */
#else
u8 readwrite = (bytesin + readoffby1) << 4 | bytesout;
spi_write(SPI_REG_CNTRL01, readwrite);
#endif
if (CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)) {
spi_write(0x1E, 5);
spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */
spi_write(0x1E, 6);
spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */
} else {
u8 readwrite = (bytesin + readoffby1) << 4 | bytesout;
spi_write(SPI_REG_CNTRL01, readwrite);
}
spi_write(SPI_REG_OPCODE, cmd);
reset_internal_fifo_pointer();