mb/google/brya/var/crota: Modify some GPIO programming
Base on bernadino 14 adl-p 20220531.pdf, configure GPIOs according to schematics. GPP_B2 => BYPASS_DET GPP_F19 => FP_USER_PRES_FP_L BUG=b:234384954 TEST= USE="project_crota" emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ic2e7ecc34912f07463e0025787fdf59c7602e40b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -20,8 +20,8 @@ static const struct pad_config override_gpio_table[] = {
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/* A23 : ESPI_CS1# ==> AUD_HP_INT_L */
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PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
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/* B2 : VRALERT# ==> NC */
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PAD_NC(GPP_B2, NONE),
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/* B2 : VRALERT# ==> BYPASS_DET */
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PAD_CFG_GPI(GPP_B2, NONE, DEEP),
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/* B3 : PROC_GP2 ==> NC */
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PAD_NC(GPP_B3, NONE),
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/* B15 : PROC_GP3 ==> AUD_RST_L */
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@ -62,8 +62,8 @@ static const struct pad_config override_gpio_table[] = {
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/* E23 : DDPA_CTRLDATA ==> NC */
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PAD_NC(GPP_E23, NONE),
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/* F19 : SRCCLKREQ6# ==> NC */
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PAD_NC(GPP_F19, NONE),
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/* F19 : SRCCLKREQ6# ==> FP_USER_PRES_FP_L */
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PAD_CFG_GPI(GPP_F19, NONE, DEEP),
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/* F20 : EXT_PWR_GATE# ==> NC */
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PAD_NC(GPP_F20, NONE),
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