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mb/google/fizz: Enable mbox command for ISL VR c-state issue 

There is a potential IMVP8 issue for KBL that affects Intersil VRs
Fizz is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.

BUG=b:65499724
BRANCH=None
TEST=Build and boot Fizz

Change-Id: Iebfda02df88ea0d2aaf79e8449b95c0eb2165c6b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/22763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Rizwan Qureshi 2017-12-07 02:10:06 +05:30 committed by Martin Roth
parent be6fd4c4b5
commit bbff157df5
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/fizz/devicetree.cb
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@ -86,6 +86,10 @@ chip soc/intel/skylake
register "PmTimerDisabled" = "1"
register "SendVrMbxCmd" = "1" # IMVP8 workaround
# Intersil VR c-state issue workaround
# send VR mailbox command for IA/GT/SA rails
register "IslVrCmd" = "2"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
register "pirqc_routing" = "PCH_IRQ11"