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x86: add rom cache variable MTRR index to tables 

Downstream payloads may need to take advantage of caching the
ROM for performance reasons. Add the ability to communicate the
variable range MTRR index to use to perform the caching enablement.

An example usage implementation would be to obtain the variable MTRR
index that covers the ROM from the coreboot tables. Then one would
disable caching and change the MTRR type from uncacheable to
write-protect and enable caching. The opposite sequence is required
to tearn down the caching.

Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2919
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2013-03-26 13:09:39 -05:00 committed by Stefan Reinauer
parent f567f16af4
commit bc07f5d935
4 changed files with 39 additions and 0 deletions
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5
src/cpu/x86/mtrr/mtrr.c
View File

@ -349,6 +349,11 @@ void x86_setup_fixed_mtrrs(void)
#if CONFIG_CACHE_ROM
static long rom_cache_mtrr = -1;
long x86_mtrr_rom_cache_var_index(void)
{
return rom_cache_mtrr;
}
void x86_mtrr_enable_rom_caching(void)
{
msr_t msr_val;

8
src/include/boot/coreboot_tables.h
View File

@ -250,6 +250,14 @@ struct lb_vboot_handoff {
uint32_t vboot_handoff_size;
};
#define LB_TAG_X86_ROM_MTRR 0x0021
struct lb_x86_rom_mtrr {
uint32_t tag;
uint32_t size;
/* The variable range MTRR index covering the ROM. */
uint32_t index;
};
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */

3
src/include/cpu/x86/mtrr.h
View File

@ -78,9 +78,12 @@ int x86_mtrr_check(void);
#if CONFIG_CACHE_ROM
void x86_mtrr_enable_rom_caching(void);
void x86_mtrr_disable_rom_caching(void);
/* Return the variable range MTRR index of the ROM cache. */
long x86_mtrr_rom_cache_var_index(void);
#else
static inline void x86_mtrr_enable_rom_caching(void) {}
static inline void x86_mtrr_disable_rom_caching(void) {}
static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
#endif /* CONFIG_CACHE_ROM */
#endif

23
src/lib/coreboot_table.c
View File

@ -40,6 +40,9 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
#if CONFIG_ARCH_X86
#include <cpu/x86/mtrr.h>
#endif
static struct lb_header *lb_table_init(unsigned long addr)
{
@ -237,6 +240,24 @@ static inline void lb_vboot_handoff(struct lb_header *header) {}
#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
#endif /* CONFIG_CHROMEOS */
static void lb_x86_rom_cache(struct lb_header *header)
{
#if CONFIG_ARCH_X86
long mtrr_index;
struct lb_x86_rom_mtrr *lb_x86_rom_mtrr;
mtrr_index = x86_mtrr_rom_cache_var_index();
if (mtrr_index < 0)
return;
lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header);
lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR;
lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr);
lb_x86_rom_mtrr->index = mtrr_index;
#endif
}
static void add_cbmem_pointers(struct lb_header *header)
{
/*
@ -539,6 +560,8 @@ unsigned long write_coreboot_table(
lb_strings(head);
/* Record our framebuffer */
lb_framebuffer(head);
/* Communicate x86 variable MTRR ROM cache information. */
lb_x86_rom_cache(head);
#if CONFIG_CHROMEOS
/* Record our GPIO settings (ChromeOS specific) */