From bc1febad5b6acef70f4fc98542261e95c4849354 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 13 Jan 2022 19:05:27 +0100
Subject: [PATCH] soc/amd/sabrina/include/southbridge: add new I2C_PAD_CTRL
 bits

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iac1b7308851c34bd1556c02af6b270e9346073e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/sabrina/include/soc/southbridge.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h
index 869af0bc87..4b25c5eda6 100644
--- a/src/soc/amd/sabrina/include/soc/southbridge.h
+++ b/src/soc/amd/sabrina/include/soc/southbridge.h
@@ -139,6 +139,9 @@
 #define   I2C_PAD_CTRL_BIAS_CRT_EN	BIT(16)
 #define   I2C_PAD_CTRL_SPARE0		BIT(17)
 #define   I2C_PAD_CTRL_SPARE1		BIT(18)
+#define   I2C_PAD_CTRL_PD_EN		BIT(19)
+#define   I2C_PAD_CTRL_COMP_SEL		BIT(20)
+#define   I2C_PAD_CTRL_RES_BIAS_EN	BIT(21)
 
 void fch_pre_init(void);
 void fch_early_init(void);