southbridge/amd/pi: Rename Avalon to Hudson

To maintain consistancy with southbridge/amd/agesa/hudson rename
pi/avalon to pi/hudson in advance of adding support for the
base hudson southbridge.

Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8251
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

src/mainboard/amd/olivehillplus/devicetree.cb

@@ -41,7 +41,7 @@ chip northbridge/amd/pi/00730F01/root_complex
 				device pci 8.0 on  end # Platform Security Processor
 			end	#chip northbridge/amd/pi/00730F01
 
-			chip southbridge/amd/pi/avalon # it is under NB/SB Link, but on the same pci bus
+			chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
 				device pci 10.0 on  end # XHCI HC0
 				device pci 11.0 on  end # SATA
 				device pci 12.0 on  end # USB
@@ -60,7 +60,7 @@ chip northbridge/amd/pi/00730F01/root_complex
 				device pci 14.3 on  end # LPC	0x439d
 				device pci 14.7 on  end # SD
 				device pci 16.0 on  end # USB
-			end	#chip southbridge/amd/pi/avalon
+			end	#chip southbridge/amd/pi/hudson
 
 			device pci 18.0 on  end
 			device pci 18.1 on  end

src/mainboard/amd/olivehillplus/dsdt.asl

@@ -37,13 +37,13 @@ DefinitionBlock (
 	#include "acpi/usb_oc.asl"
 
 	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/pi/avalon/acpi/pcie.asl>
+	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
 
 	/* Describe the processor tree (\_PR) */
 	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/pi/avalon/acpi/sleepstates.asl>
+	#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
 
 	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
 	#include "acpi/sleep.asl"
@@ -68,16 +68,16 @@ DefinitionBlock (
 			#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
 
 			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/pi/avalon/acpi/fch.asl>
+			#include <southbridge/amd/pi/hudson/acpi/fch.asl>
 		}
 
 		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/pi/avalon/acpi/pci_int.asl>
+		#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
 
 	} /* End \_SB scope */
 
 	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/pi/avalon/acpi/smbus.asl>
+	#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
 
 	/* Define the General Purpose Events for the platform */
 	#include "acpi/gpe.asl"

src/mainboard/amd/olivehillplus/mptable.c

@@ -27,7 +27,7 @@
 #include <cpu/amd/amdfam15.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/avalon/hudson.h> /* pm_ioread() */
+#include <southbridge/amd/pi/hudson/hudson.h> /* pm_ioread() */
 
 u8 picr_data[0x54] = {
 	0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,

src/mainboard/amd/olivehillplus/romstage.c

@@ -34,7 +34,7 @@
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/avalon/hudson.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
 #include <cpu/amd/pi/s3_resume.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/southbridge/amd/pi/Kconfig

@@ -17,4 +17,4 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
 
-source src/southbridge/amd/pi/avalon/Kconfig
+source src/southbridge/amd/pi/hudson/Kconfig

src/southbridge/amd/pi/Makefile.inc

@@ -16,4 +16,4 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += avalon
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson

src/southbridge/amd/pi/hudson/Kconfig

@@ -27,7 +27,7 @@ if SOUTHBRIDGE_AMD_PI_AVALON
 
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
-	default "southbridge/amd/pi/avalon/bootblock.c"
+	default "southbridge/amd/pi/hudson/bootblock.c"
 
 config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT
 	bool
@@ -172,7 +172,7 @@ config HUDSON_AHCI_ROM
 config AHCI_ROM_FILE
 	string "AHCI ROM path and filename"
 	depends on HUDSON_AHCI_ROM
-	default "src/southbridge/amd/pi/avalon/ahci.bin"
+	default "src/southbridge/amd/pi/hudson/ahci.bin"
 
 endif
 
@@ -186,11 +186,11 @@ config RAID_ROM_ID
 
 config RAID_ROM_FILE
 	string "RAID ROM path and filename"
-	default "src/southbridge/amd/pi/avalon/raid.bin"
+	default "src/southbridge/amd/pi/hudson/raid.bin"
 
 config RAID_MISC_ROM_FILE
 	string "RAID Misc ROM path and filename"
-	default "src/southbridge/amd/pi/avalon/misc.bin"
+	default "src/southbridge/amd/pi/hudson/misc.bin"
 
 config RAID_MISC_ROM_POSITION
 	hex "RAID Misc ROM Position"

src/southbridge/amd/pi/hudson/Makefile.inc

@@ -28,7 +28,7 @@
 #
 #*****************************************************************************
 
-INCLUDES += -Isrc/southbridge/amd/pi/avalon
+INCLUDES += -Isrc/southbridge/amd/pi/hudson
 
 romstage-y += smbus.c smbus_spd.c
 ramstage-y += hudson.c

src/southbridge/amd/pi/hudson/chip.h

@@ -17,10 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef AVALON_CHIP_H
-#define AVALON_CHIP_H
+#ifndef HUDSON_CHIP_H
+#define HUDSON_CHIP_H
 
-struct southbridge_amd_pi_avalon_config
+struct southbridge_amd_pi_hudson_config
 {
 	#if 1
 	u32 ide0_enable : 1;
@@ -32,4 +32,4 @@ struct southbridge_amd_pi_avalon_config
 	#endif
 };
 
-#endif /* AVALON_CHIP_H */
+#endif /* HUDSON_CHIP_H */

src/southbridge/amd/pi/hudson/hudson.c

@@ -33,7 +33,7 @@
 
 /* Offsets from ACPI_MMIO_BASE
  * This is defined by AGESA, but we don't include AGESA headers to avoid
- * polluting the namesace.
+ * polluting the namespace.
  */
 #define PM_MMIO_BASE 0xfed80300
 
@@ -132,7 +132,7 @@ static void hudson_final(void *chip_info)
 {
 }
 
-struct chip_operations southbridge_amd_pi_avalon_ops = {
+struct chip_operations southbridge_amd_pi_hudson_ops = {
 	CHIP_NAME("ATI HUDSON")
 	.enable_dev = hudson_enable,
 	.init = hudson_init,

src/southbridge/amd/pi/hudson/sd.c

@@ -31,8 +31,8 @@ static void sd_init(struct device *dev)
 
 	stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
 
-	struct southbridge_amd_pi_avalon_config *sd_chip =
-		(struct southbridge_amd_pi_avalon_config *)(dev->chip_info);
+	struct southbridge_amd_pi_hudson_config *sd_chip =
+		(struct southbridge_amd_pi_hudson_config *)(dev->chip_info);
 
 	if (sd_chip->sd_mode == 3) {	/* SD 3.0 mode */
 		pci_write_config32(dev, 0xA4, 0x31FEC8B2);

src/vendorcode/amd/pi/00730F01/Makefile.inc

@@ -47,7 +47,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
 AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
 AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
 
-AGESA_INC += -I$(src)/southbridge/amd/pi/avalon
+AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
 
 AGESA_INC += -I$(src)/arch/x86/include
 AGESA_INC += -I$(src)/include