libpayload/x86: Try to discover invariant TSC rate
We can skip the PIT-based TSC calibration if we can derive the invariant TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled, which is the default, for instance, on Coffee Lake CPUs. This implementation should cover all Intel Core i processors at least. For older processors, we fall back to the PIT calibration. Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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@ -33,6 +33,10 @@
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#include <libpayload.h>
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#include <arch/rdtsc.h>
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#include <arch/cpuid.h>
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#include <arch/msr.h>
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#define MSR_PLATFORM_INFO 0xce
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/**
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* @ingroup arch
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@ -41,11 +45,11 @@
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uint32_t cpu_khz;
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/**
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* Calculate the speed of the processor for use in delays.
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* @brief Measure the speed of the processor for use in delays
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*
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* @return The CPU speed in kHz.
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*/
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unsigned int get_cpu_speed(void)
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static unsigned int calibrate_pit(void)
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{
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unsigned long long start, end;
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const uint32_t clock_rate = 1193182; // 1.193182 MHz
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@ -71,7 +75,116 @@ unsigned int get_cpu_speed(void)
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* clock_rate / (interval * 1000). Multiply that by the number of
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* measured clocks to get the kHz value.
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*/
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cpu_khz = (end - start) * clock_rate / (1000 * interval);
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return (end - start) * clock_rate / (1000 * interval);
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}
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/**
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* @brief Calculates the core clock frequency via CPUID 0x15
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*
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* Newer Intel CPUs report their core clock in CPUID leaf 0x15. Early models
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* supporting this leaf didn't provide the nominal crystal frequency in ecx,
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* hence we use hard coded values for them.
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*/
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static int get_cpu_khz_xtal(void)
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{
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uint32_t ecx, edx, num, denom;
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uint64_t nominal;
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if (cpuid_max() < 0x15)
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return -1;
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cpuid(0x15, denom, num, ecx, edx);
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if (denom == 0 || num == 0)
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return -1;
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if (ecx != 0) {
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nominal = ecx;
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} else {
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if (cpuid_family() != 6)
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return -1;
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switch (cpuid_model()) {
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case SKYLAKE_U_Y:
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case SKYLAKE_S_H:
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case KABYLAKE_U_Y:
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case KABYLAKE_S_H:
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nominal = 24000000;
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break;
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case APOLLOLAKE:
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nominal = 19200000;
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break;
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default:
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return -1;
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}
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}
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return nominal * num / denom / 1000;
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}
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/**
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* @brief Returns three times the bus clock in kHz
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*
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* The result of calculations with the returned value shall be divided by 3.
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* This helps to avoid rounding errors.
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*/
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static int get_bus_khz_x3(void)
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{
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if (cpuid_family() != 6)
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return -1;
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switch (cpuid_model()) {
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case NEHALEM:
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return 400 * 1000; /* 133 MHz */
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case SANDYBRIDGE:
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case IVYBRIDGE:
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case HASWELL:
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case HASWELL_U:
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case HASWELL_GT3E:
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case BROADWELL:
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case BROADWELL_U:
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return 300 * 1000; /* 100 MHz */
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default:
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return -1;
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}
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}
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/**
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* @brief Returns the calculated CPU frequency
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*
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* Over the years, multiple ways to discover the CPU frequency have been
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* exposed through CPUID and MSRs. Try the most recent and accurate first
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* (crystal information in CPUID leaf 0x15) and then fall back to older
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* methods.
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*
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* This should cover all Intel Core i processors at least. For older
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* processors we fall back to the PIT calibration.
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*/
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static int get_cpu_khz_fast(void)
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{
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/* Try core crystal clock frequency first (supposed to be more accurate). */
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const int cpu_khz_xtal = get_cpu_khz_xtal();
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if (cpu_khz_xtal > 0)
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return cpu_khz_xtal;
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/* Try `bus clock * speedstep multiplier`. */
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const int bus_x3 = get_bus_khz_x3();
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if (bus_x3 <= 0)
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return -1;
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/*
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* Systems with an invariant TSC report the multiplier (maximum
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* non-turbo ratio) in MSR_PLATFORM_INFO[15:8].
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*/
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const unsigned int mult = _rdmsr(MSR_PLATFORM_INFO) >> 8 & 0xff;
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return bus_x3 * mult / 3;
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}
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unsigned int get_cpu_speed(void)
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{
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const int cpu_khz_fast = get_cpu_khz_fast();
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if (cpu_khz_fast > 0)
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cpu_khz = (unsigned int)cpu_khz_fast;
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else
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cpu_khz = calibrate_pit();
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return cpu_khz;
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}
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