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nb/intel/sandybridge: add and use defines for ME base and mask registers 

Timeless build results in identical image for X230.

Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Felix Held 2019-12-28 18:44:06 +01:00
parent 4902fee441
commit bc3668a468
3 changed files with 16 additions and 13 deletions
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2
src/northbridge/intel/sandybridge/finalize.c
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@ -24,7 +24,7 @@ void intel_sandybridge_finalize_smm(void)
pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0);
pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2);
pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0);
pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
pci_or_config32(PCI_DEV_SNB, MEMASK, 1 << 10);
pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0);
pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0);
pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0);

24
src/northbridge/intel/sandybridge/raminit_common.c
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@ -585,34 +585,34 @@ void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)
pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg);
if (me_uma_size) {
reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x7c);
reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK + 4);
val = (0x80000 - me_uma_size) & 0xfffff000;
reg = (reg & ~0x000fffff) | (val >> 12);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x7c, reg);
pci_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK + 4, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MEMASK + 4, reg);
// ME base
reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x70);
reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE);
val = mestolenbase & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x70, reg);
pci_write_config32(PCI_DEV(0, 0, 0), 0x70, reg);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MEBASE, reg);
reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x74);
reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE + 4);
val = mestolenbase & 0xfffff000;
reg = (reg & ~0x000fffff) | (val >> 12);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x74, reg);
pci_write_config32(PCI_DEV(0, 0, 0), 0x74, reg);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE + 4, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MEBASE + 4, reg);
// ME mask
reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x78);
reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK);
val = (0x80000 - me_uma_size) & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem
reg = (reg & ~0x800) | (1 << 11); // set ME memory enable
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x78, reg);
pci_write_config32(PCI_DEV(0, 0, 0), 0x78, reg);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MEMASK, reg);
}
}

3
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -82,6 +82,9 @@ enum platform_type {
#define PAVPC 0x58 /* Protected Audio Video Path Control */
#define DPR 0x5c /* DMA Protected Range */
#define MEBASE 0x70
#define MEMASK 0x78
#define PAM0 0x80
#define PAM1 0x81
#define PAM2 0x82