soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add ELOG wake sources for ports 13-24, if they exist. Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -149,6 +149,18 @@
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#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d
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#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e
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#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f
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#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20
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#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21
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#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22
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#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23
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#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24
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#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25
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#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26
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#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27
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#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28
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#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29
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#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a
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#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b
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struct elog_event_data_wake {
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u8 source;
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@ -121,7 +121,7 @@ static void pch_log_pme_internal_wake_source(void)
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#define RP_PME_STS_BIT (1 << 16)
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static void pch_log_rp_wake_source(void)
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{
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size_t i;
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size_t i, maxports;
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev;
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#else
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@ -142,9 +142,23 @@ static void pch_log_rp_wake_source(void)
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{ PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 },
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{ PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 },
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{ PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 },
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{ PCH_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 },
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{ PCH_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 },
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{ PCH_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 },
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{ PCH_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 },
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{ PCH_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 },
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{ PCH_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 },
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{ PCH_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 },
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{ PCH_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 },
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{ PCH_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 },
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{ PCH_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 },
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{ PCH_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 },
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{ PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 },
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};
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for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) {
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maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info));
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for (i = 0; i < maxports; i++) {
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dev = pme_status_info[i].dev;
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if (!dev)
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