mainboard/google/fizz: Enable Devslp for SATA port 1
This patch is to enable the support of device sleep for SATA port 1 and disable unused SATA port 0. BUG=b:65808359 BRANCH=None TEST=Ran "suspend_stress_test -c 2500" and passed the test. Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
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@ -56,8 +56,8 @@ chip soc/intel/skylake
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register "EnableSata" = "1"
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register "SataSalpSupport" = "1"
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register "SataMode" = "1"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsDevSlp[1]" = "1"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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@ -179,7 +179,7 @@ static const struct pad_config gpio_table[] = {
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/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,
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NF1), /* DB_PCIE_SATA#_DET */
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/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
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/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */
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/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
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/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */
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/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* TP328 */
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/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),
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