get arima hdama building again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
66e7d5e5f4
commit
bc3f2f0641
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@ -46,6 +46,26 @@ driver mainboard.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
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end
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else
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makerule ./auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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else
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##
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## Romcc output
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##
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@ -68,13 +88,27 @@ makerule ./auto.inc
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action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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@ -87,8 +121,11 @@ else
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ldscript /cpu/x86/32bit/reset32.lds
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end
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if USE_DCACHE_RAM
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else
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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end
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##
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## Include an id string (For safe flashing)
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@ -96,20 +133,44 @@ mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if USE_DCACHE_RAM
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/amd/car/cache_as_ram.inc
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end
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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else
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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initobject auto.o
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else
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mainboardinit ./auto.inc
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end
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else
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##
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## Setup RAM
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##
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@ -119,11 +180,11 @@ mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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end
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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# config for arima/hdama
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@ -51,7 +51,9 @@ uses OBJCOPY
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_LOGICAL_CPUS
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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uses CONFIG_USE_INIT
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###
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@ -120,6 +122,14 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
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##
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default CONFIG_IOAPIC=1
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM=1
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default DCACHE_RAM_BASE=0xcf000
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default DCACHE_RAM_SIZE=0x1000
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default CONFIG_USE_INIT=0
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#VGA
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default CONFIG_CONSOLE_VGA=1
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default CONFIG_PCI_ROM_RUN=1
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@ -83,50 +83,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
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}
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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{
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/* Routing Table Node i
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*
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* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
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* i: 0, 1, 2, 3, 4, 5, 6, 7
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*
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* [ 0: 3] Request Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [11: 8] Response Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [19:16] Broadcast route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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*/
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uint32_t ret = 0x00010101; /* default row entry */
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/* CPU0 LDT1 <-> LDT1 CPU1 */
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static const unsigned int rows_2p[2][2] = {
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{ 0x00050101, 0x00010404 },
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{ 0x00010404, 0x00050101 }
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};
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if (maxnodes > 2) {
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print_spew("this mainboard is only designed for 2 cpus\r\n");
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maxnodes = 2;
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}
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if (!(node >= maxnodes || row >= maxnodes)) {
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ret = rows_2p[node][row];
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}
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return ret;
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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@ -0,0 +1,222 @@
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#define ASSEMBLY 1
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#define __ROMCC__
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include <cpu/amd/model_fxx_rev.h>
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#include "lib/delay.c"
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#if CONFIG_USE_INIT == 0
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#include "lib/memcpy.c"
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#endif
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "superio/nsc/pc87360/pc87360_early_serial.c"
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#include "cpu/amd/mtrr/amd_earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
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#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
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/*
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* GPIO28 of 8111 will control H0_MEMRESET_L
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* GPIO29 of 8111 will control H1_MEMRESET_L
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*/
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static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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else {
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/* Ensure the CPU has controll of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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if (is_cpu_pre_c0()) {
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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udelay(90);
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}
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#define QRANK_DIMM_SUPPORT 1
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/resourcemap.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#if CONFIG_LOGICAL_CPUS==1
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#define SET_NB_CFG_54 1
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#endif
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#include "cpu/amd/dualcore/dualcore.c"
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#define FIRST_CPU 1
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#define SECOND_CPU 1
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
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#include "cpu/amd/car/copy_and_run.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#if USE_FALLBACK_IMAGE == 1
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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unsigned last_boot_normal_x = last_boot_normal();
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/* Is this a cpu only reset? or Is this a secondary cpu? */
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if ((cpu_init_detectedx) || (!boot_cpu())) {
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if (last_boot_normal_x) {
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goto normal_image;
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} else {
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goto fallback_image;
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}
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}
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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/* Is this a deliberate reset by the bios */
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if (bios_reset_detected() && last_boot_normal_x) {
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goto normal_image;
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}
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/* This is the primary cpu how should I boot? */
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else if (do_normal_boot()) {
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goto normal_image;
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}
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else {
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goto fallback_image;
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}
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normal_image:
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__asm__ volatile ("jmp __normal_image"
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: /* outputs */
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: "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
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);
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fallback_image:
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;
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}
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#endif
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void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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#if USE_FALLBACK_IMAGE == 1
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failover_process(bist, cpu_init_detectedx);
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#endif
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real_main(bist, cpu_init_detectedx);
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}
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void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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static const struct mem_controller cpu[] = {
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
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.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
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},
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#if CONFIG_MAX_PHYSICAL_CPUS > 1
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{
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.node_id = 1,
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
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.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
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},
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#endif
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};
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int needs_reset;
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if (bist == 0) {
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init_cpus(cpu_init_detectedx);
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}
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pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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setup_default_resource_map();
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needs_reset = setup_coherent_ht_domain();
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#if CONFIG_LOGICAL_CPUS==1
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// It is said that we should start core1 after all core0 launched
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start_other_cores();
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#endif
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// automatically set that for you, but you might meet tight space
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needs_reset |= ht_setup_chains_x();
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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}
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enable_smbus();
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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post_cache_as_ram();
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}
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