soc/amd/picasso: Change all remaining soc names
Convert all remaining stoneyridge names to picasso. Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Marshall Dawson
Martin Roth
parent
30cf155168
commit
bc4c903c1f
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@ -185,9 +185,9 @@ config STONEYRIDGE_GEC_FWM_FILE
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config AMD_PUBKEY_FILE
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string "AMD public Key"
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default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin"
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default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin"
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config STONEYRIDGE_SATA_MODE
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config PICASSO_SATA_MODE
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int "SATA Mode"
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default 0
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range 0 6
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@ -203,33 +203,33 @@ config STONEYRIDGE_SATA_MODE
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6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
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comment "NATIVE"
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depends on STONEYRIDGE_SATA_MODE = 0
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depends on PICASSO_SATA_MODE = 0
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comment "AHCI"
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depends on STONEYRIDGE_SATA_MODE = 2
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depends on PICASSO_SATA_MODE = 2
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comment "LEGACY IDE"
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depends on STONEYRIDGE_SATA_MODE = 3
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depends on PICASSO_SATA_MODE = 3
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comment "IDE to AHCI"
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depends on STONEYRIDGE_SATA_MODE = 4
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depends on PICASSO_SATA_MODE = 4
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comment "AHCI7804"
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depends on STONEYRIDGE_SATA_MODE = 5
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depends on PICASSO_SATA_MODE = 5
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comment "IDE to AHCI7804"
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depends on STONEYRIDGE_SATA_MODE = 6
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depends on PICASSO_SATA_MODE = 6
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if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
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if PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5
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config AHCI_ROM_ID
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string "AHCI device PCI IDs"
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default "1022,7801" if STONEYRIDGE_SATA_MODE = 2
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default "1022,7804" if STONEYRIDGE_SATA_MODE = 5
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default "1022,7801" if PICASSO_SATA_MODE = 2
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default "1022,7804" if PICASSO_SATA_MODE = 5
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endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
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endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5
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config STONEYRIDGE_LEGACY_FREE
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config PICASSO_LEGACY_FREE
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bool "System is legacy free"
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help
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Select y if there is no keyboard controller in the system.
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@ -242,22 +242,22 @@ config SERIRQ_CONTINUOUS_MODE
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Set this option to y for serial IRQ in continuous mode.
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Otherwise it is in quiet mode.
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config STONEYRIDGE_ACPI_IO_BASE
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config PICASSO_ACPI_IO_BASE
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hex
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default 0x400
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help
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Base address for the ACPI registers.
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This value must match the hardcoded value of AGESA.
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config STONEYRIDGE_UART
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bool "UART controller on Stoney Ridge"
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config PICASSO_UART
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bool "UART controller on Picasso"
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default n
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select DRIVERS_UART_8250MEM
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select DRIVERS_UART_8250MEM_32
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select NO_UART_ON_SUPERIO
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select UART_OVERRIDE_REFCLK
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help
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There are two UART controllers in Stoney Ridge.
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There are two UART controllers in Picasso.
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The UART registers are memory-mapped. UART
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controller 0 registers range from FEDC_6000h
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to FEDC_6FFFh. UART controller 1 registers
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@ -52,7 +52,7 @@ romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += smbus.c
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romstage-y += ramtop.c
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romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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romstage-$(CONFIG_PICASSO_UART) += uart.c
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romstage-y += tsc_freq.c
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romstage-y += southbridge.c
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romstage-$(CONFIG_SPI_FLASH) += spi.c
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@ -63,12 +63,12 @@ verstage-y += i2c.c
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verstage-y += monotonic_timer.c
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verstage-y += pmutil.c
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verstage-y += reset.c
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verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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verstage-$(CONFIG_PICASSO_UART) += uart.c
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verstage-y += tsc_freq.c
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verstage-$(CONFIG_SPI_FLASH) += spi.c
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postcar-y += monotonic_timer.c
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postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
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postcar-$(CONFIG_PICASSO_UART) += uart.c
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postcar-y += ramtop.c
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postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
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postcar-y += tsc_freq.c
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@ -90,7 +90,7 @@ ramstage-y += smbus.c
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ramstage-y += ramtop.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
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ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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ramstage-$(CONFIG_PICASSO_UART) += uart.c
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ramstage-y += usb.c
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ramstage-y += tsc_freq.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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@ -117,7 +117,7 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi
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# +-----------+
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#
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# EC ROM should be 64K aligned.
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STONEYRIDGE_FWM_POSITION=$(call int-add, \
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PICASSO_FWM_POSITION=$(call int-add, \
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$(call int-subtract, 0xffffffff \
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$(call int-shift-left, \
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0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
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@ -247,7 +247,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \
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$(OPT_SMUSCS_FILE) \
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--combo-capable \
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--flashsize $(CONFIG_ROM_SIZE) \
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--location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \
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--location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \
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--output $@
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ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
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@ -255,23 +255,23 @@ PHONY+=add_amdfw
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INTERMEDIATE+=add_amdfw
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# Calculate firmware position inside the ROM
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STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \
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PICASSO_FWM_ROM_POSITION=$(call int-add, \
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$(call int-subtract, $(CONFIG_ROM_SIZE) \
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$(call int-shift-left, \
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0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000)
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add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom
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printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \
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"$(STONEYRIDGE_FWM_ROM_POSITION)"
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"$(PICASSO_FWM_ROM_POSITION)"
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dd if=$(obj)/amdfw.rom \
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of=$(obj)/coreboot.pre conv=notrunc bs=1 \
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seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1
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seek=$(PICASSO_FWM_ROM_POSITION) >/dev/null 2>&1
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else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
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cbfs-files-y += apu/amdfw
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apu/amdfw-file := $(obj)/amdfw.rom
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apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION)
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apu/amdfw-position := $(PICASSO_FWM_POSITION)
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apu/amdfw-type := raw
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endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
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@ -75,7 +75,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
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{
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acpi_header_t *header = &(fadt->header);
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printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE);
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printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE);
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/* Prepare the header */
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memset((void *)fadt, 0, sizeof(acpi_fadt_t));
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@ -241,7 +241,7 @@ void generate_cpu_entries(struct device *device)
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{
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int cores, cpu;
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/* Stoney Ridge is single node, just report # of cores */
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/* Picasso is single node, just report # of cores */
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cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
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cores++; /* number of cores is CmpCap+1 */
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@ -32,14 +32,14 @@
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#include "chip.h"
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/* Supplied by i2c.c */
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extern struct device_operations stoneyridge_i2c_mmio_ops;
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extern struct device_operations picasso_i2c_mmio_ops;
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extern const char *i2c_acpi_name(const struct device *dev);
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struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = stoney_init_cpus,
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.init = picasso_init_cpus,
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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};
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@ -132,7 +132,7 @@ static void enable_dev(struct device *dev)
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sb_enable(dev);
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else if (dev->path.type == DEVICE_PATH_MMIO)
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if (i2c_acpi_name(dev) != NULL)
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dev->ops = &stoneyridge_i2c_mmio_ops;
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dev->ops = &picasso_i2c_mmio_ops;
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}
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static void soc_init(void *chip_info)
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@ -147,8 +147,8 @@ static void soc_final(void *chip_info)
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fam15_finalize(chip_info);
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}
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struct chip_operations soc_amd_stoneyridge_ops = {
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CHIP_NAME("AMD StoneyRidge SOC")
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struct chip_operations soc_amd_picasso_ops = {
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CHIP_NAME("AMD Picasso SOC")
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.enable_dev = enable_dev,
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.init = soc_init,
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.final = soc_final
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@ -27,9 +27,9 @@
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#define MAX_DRAM_CH 1
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#define MAX_DIMMS_PER_CH 2
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#define STONEY_I2C_DEV_MAX 4
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#define PICASSO_I2C_DEV_MAX 4
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struct soc_amd_stoneyridge_config {
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struct soc_amd_picasso_config {
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u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
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enum {
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DRAM_CONTENTS_KEEP,
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@ -59,7 +59,7 @@ struct soc_amd_stoneyridge_config {
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* register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
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*/
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u8 i2c_scl_reset;
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struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX];
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struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX];
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u8 stapm_percent;
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u32 stapm_time_ms;
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u32 stapm_power_mw;
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@ -74,7 +74,7 @@ struct soc_amd_stoneyridge_config {
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u8 lvds_poseq_blon_to_varybl;
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};
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typedef struct soc_amd_stoneyridge_config config_t;
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typedef struct soc_amd_picasso_config config_t;
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extern struct device_operations pci_domain_ops;
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@ -105,7 +105,7 @@ static const struct mp_ops mp_ops = {
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.post_mp_init = enable_smi_generation,
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};
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void stoney_init_cpus(struct device *dev)
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void picasso_init_cpus(struct device *dev)
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{
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/* Clear for take-off */
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if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
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@ -46,7 +46,7 @@ uintptr_t dw_i2c_base_address(unsigned int bus)
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return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0;
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}
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static const struct soc_amd_stoneyridge_config *get_soc_config(void)
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static const struct soc_amd_picasso_config *get_soc_config(void)
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{
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const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
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@ -61,7 +61,7 @@ static const struct soc_amd_stoneyridge_config *get_soc_config(void)
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const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
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{
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const struct soc_amd_stoneyridge_config *config;
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const struct soc_amd_picasso_config *config;
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if (bus >= ARRAY_SIZE(i2c_bus_address))
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return NULL;
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@ -107,7 +107,7 @@ int dw_i2c_soc_dev_to_bus(struct device *dev)
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static void dw_i2c_soc_init(bool is_early_init)
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{
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size_t i;
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const struct soc_amd_stoneyridge_config *config;
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const struct soc_amd_picasso_config *config;
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config = get_soc_config();
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@ -135,7 +135,7 @@ void i2c_soc_init(void)
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dw_i2c_soc_init(false);
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}
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struct device_operations stoneyridge_i2c_mmio_ops = {
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struct device_operations picasso_i2c_mmio_ops = {
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/* TODO(teravest): Move I2C resource info here. */
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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@ -188,7 +188,7 @@ static void restore_i2c_pin_registers(uint8_t gpio,
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/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */
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void sb_reset_i2c_slaves(void)
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{
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const struct soc_amd_stoneyridge_config *cfg;
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const struct soc_amd_picasso_config *cfg;
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const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
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struct soc_amd_i2c_save save_table[saved_pins_count];
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uint8_t i, j, control;
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@ -20,7 +20,7 @@
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#include <arch/acpi.h>
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#if CONFIG(STONEYRIDGE_LEGACY_FREE)
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#if CONFIG(PICASSO_LEGACY_FREE)
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#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
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#else
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#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
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@ -29,7 +29,7 @@
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#define SOC_EARLY_VMTRR_CAR_HEAP 2
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#define SOC_EARLY_VMTRR_TEMPRAM 3
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void stoney_init_cpus(struct device *dev);
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void picasso_init_cpus(struct device *dev);
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void check_mca(void);
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#endif /* __PICASSO_CPU_H__ */
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@ -61,16 +61,16 @@
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/* I/O Ranges */
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#define ACPI_SMI_CTL_PORT 0xb2
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#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE
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#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
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#define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE
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#define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */
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#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */
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#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */
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#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
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#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
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#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
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#define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */
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#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x08) /* 6 bytes */
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#define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x10) /* 8 bytes */
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#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */
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#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */
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#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
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#define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x18) /* 4 bytes */
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#define SMB_BASE_ADDR 0xb00
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#define PM2_INDEX 0xcd0
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#define PM2_DATA 0xcd1
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@ -316,7 +316,7 @@
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#define RST_CMD BIT(2)
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#define SYS_RST BIT(1)
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struct stoneyridge_aoac {
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struct picasso_aoac {
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int enable;
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int status;
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};
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@ -187,7 +187,7 @@ asmlinkage void car_stage_entry(void)
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void SetMemParams(AMD_POST_PARAMS *PostParams)
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{
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const struct soc_amd_stoneyridge_config *cfg;
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const struct soc_amd_picasso_config *cfg;
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const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
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if (!dev || !dev->chip_info) {
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@ -224,7 +224,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams)
|
|||
|
||||
void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
|
||||
{
|
||||
const struct soc_amd_stoneyridge_config *cfg;
|
||||
const struct soc_amd_picasso_config *cfg;
|
||||
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
|
||||
struct _PLATFORM_CONFIGURATION *platform;
|
||||
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
* waiting for each device to become available, a single delay will be
|
||||
* executed.
|
||||
*/
|
||||
const static struct stoneyridge_aoac aoac_devs[] = {
|
||||
const static struct picasso_aoac aoac_devs[] = {
|
||||
{ (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2),
|
||||
(FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) },
|
||||
{ FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA },
|
||||
|
|
@ -56,22 +56,22 @@ const static struct stoneyridge_aoac aoac_devs[] = {
|
|||
|
||||
static int is_sata_config(void)
|
||||
{
|
||||
return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE)
|
||||
|| (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE));
|
||||
return !((SataNativeIde == CONFIG_PICASSO_SATA_MODE)
|
||||
|| (SataLegacyIde == CONFIG_PICASSO_SATA_MODE));
|
||||
}
|
||||
|
||||
static inline int sb_sata_enable(void)
|
||||
{
|
||||
/* True if IDE or AHCI. */
|
||||
return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) ||
|
||||
(SataAhci == CONFIG_STONEYRIDGE_SATA_MODE);
|
||||
return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) ||
|
||||
(SataAhci == CONFIG_PICASSO_SATA_MODE);
|
||||
}
|
||||
|
||||
static inline int sb_ide_enable(void)
|
||||
{
|
||||
/* True if IDE or LEGACY IDE. */
|
||||
return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) ||
|
||||
(SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE);
|
||||
return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) ||
|
||||
(SataLegacyIde == CONFIG_PICASSO_SATA_MODE);
|
||||
}
|
||||
|
||||
void SetFchResetParams(FCH_RESET_INTERFACE *params)
|
||||
|
|
@ -91,11 +91,11 @@ void SetFchEnvParams(FCH_INTERFACE *params)
|
|||
{
|
||||
const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
|
||||
params->AzaliaController = AzEnable;
|
||||
params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
|
||||
params->SataClass = CONFIG_PICASSO_SATA_MODE;
|
||||
if (dev && dev->enabled) {
|
||||
params->SataEnable = is_sata_config();
|
||||
params->IdeEnable = !params->SataEnable;
|
||||
params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE ==
|
||||
params->SataIdeMode = (CONFIG_PICASSO_SATA_MODE ==
|
||||
SataLegacyIde);
|
||||
} else {
|
||||
params->SataEnable = FALSE;
|
||||
|
|
@ -227,7 +227,7 @@ static void sb_lpc_decode(void)
|
|||
| DECODE_ENABLE_ADLIB_PORT;
|
||||
|
||||
/* Decode SIOs at 2E/2F and 4E/4F */
|
||||
if (CONFIG(STONEYRIDGE_LEGACY_FREE))
|
||||
if (CONFIG(PICASSO_LEGACY_FREE))
|
||||
tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
|
||||
|
||||
lpc_enable_decode(tmp);
|
||||
|
|
|
|||
Loading…
Reference in New Issue