soc/amd/picasso: Generate ACPI pstate and cstate objects in cb
Add code to generate p-state and c-state SSDT objects to coreboot. Publish objects generated in native coreboot, rather than the ones created by FSP binary. BUG=b:155307433 TEST=Boot morphius to shell and extract and compare objects created in coreboot with tables generated by FSP. Confirm they are equivalent. BRANCH=Zork Change-Id: I5f4db3c0c2048ea1d6c6ce55f5e252cb15598514 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Jason Glenesk
Furquan Shaikh
parent
ebd234e059
commit
bc5214342f
5 changed files with 260 additions and 13 deletions
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@ -12,13 +12,16 @@
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#define CPUID_EXT_PM 0x80000007
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#define CPUID_MODEL 1
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#define CPUID_EBX_CORE_ID 0x8000001E
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#define CPUID_EBX_THREADS_SHIFT 8
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#define CPUID_EBX_THREADS_MASK (0xFF << CPUID_EBX_THREADS_SHIFT)
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#define MC4_MISC0 0x00000413
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#define MC4_MISC1 0xC0000408
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#define MC4_MISC2 0xC0000409
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#define FS_Base 0xC0000100
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#define HWCR_MSR 0xC0010015
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#define HWCR_MSR 0xC0010015
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#define SMM_LOCK (1 << 0)
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#define NB_CFG_MSR 0xC001001f
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#define NB_CFG_MSR 0xC001001f
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#define FidVidStatus 0xC0010042
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#define MC1_CTL_MASK 0xC0010045
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#define MC4_CTL_MASK 0xC0010048
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@ -30,6 +33,9 @@
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#define PS_LIM_REG 0xC0010061
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/* P-state Maximum Value shift position */
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#define PS_MAX_VAL_SHFT 4
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#define PS_LIM_MAX_VAL_MASK (0x7 << PS_MAX_VAL_SHFT)
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#define MAX_PSTATES 8
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/* P-state Control Register */
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#define PS_CTL_REG 0xC0010062
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/* P-state Control Register CMD Mask OFF */
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@ -43,11 +49,15 @@
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#define PSTATE_2_MSR 0xC0010066
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#define PSTATE_3_MSR 0xC0010067
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#define PSTATE_4_MSR 0xC0010068
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/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
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#define SERIAL_VID_DECODE_MICROVOLTS 6250
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#define SERIAL_VID_MAX_MICROVOLTS 1550000L
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#define MSR_PATCH_LOADER 0xC0010020
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#define MSR_COFVID_STS 0xC0010071
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#define MSR_CSTATE_ADDRESS 0xC0010073
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#define MSR_CSTATE_ADDRESS_MASK 0xFFFF
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#define OSVW_ID_Length 0xC0010140
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#define OSVW_Status 0xC0010141
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@ -354,6 +354,14 @@ config ACPI_BERT_SIZE
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Specify the amount of DRAM reserved for gathering the data used to
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generate the ACPI table.
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config ACPI_SSDT_PSD_INDEPENDENT
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bool "Allow core p-state independent transitions"
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default y
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help
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AMD recommends the ACPI _PSD object to be configured to cause
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cores to transition between p-states independently. A vendor may
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choose to generate _PSD object to allow cores to transition together.
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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select ALWAYS_LOAD_OPROM
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@ -12,6 +12,7 @@
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#include <device/pci_ops.h>
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#include <arch/ioapic.h>
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#include <arch/smp/mpspec.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/smm.h>
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#include <cbmem.h>
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#include <device/device.h>
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@ -21,6 +22,7 @@
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#include <soc/acpi.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/msr.h>
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#include <soc/southbridge.h>
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#include <soc/nvs.h>
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#include <soc/gpio.h>
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@ -166,20 +168,220 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_gpe0_blk.addrh = 0x0;
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}
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static uint32_t get_pstate_core_freq(msr_t pstate_def)
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{
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uint32_t core_freq, core_freq_mul, core_freq_div;
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bool valid_freq_divisor;
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/* Core frequency multiplier */
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core_freq_mul = pstate_def.lo & PSTATE_DEF_LO_FREQ_MUL_MASK;
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/* Core frequency divisor ID */
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core_freq_div =
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(pstate_def.lo & PSTATE_DEF_LO_FREQ_DIV_MASK) >> PSTATE_DEF_LO_FREQ_DIV_SHIFT;
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if (core_freq_div == 0) {
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return 0;
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} else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN)
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&& (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) {
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/* Allow 1/8 integer steps for this range */
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valid_freq_divisor = 1;
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} else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX)
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&& (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
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/* Only allow 1/4 integer steps for this range */
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valid_freq_divisor = 1;
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} else {
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valid_freq_divisor = 0;
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}
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if (valid_freq_divisor) {
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/* 25 * core_freq_mul / (core_freq_div / 8) */
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core_freq =
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((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
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} else {
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printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
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core_freq_div);
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core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul);
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}
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return core_freq;
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}
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static uint32_t get_pstate_core_power(msr_t pstate_def)
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{
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uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
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/* Core voltage ID */
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core_vid =
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(pstate_def.lo & PSTATE_DEF_LO_CORE_VID_MASK) >> PSTATE_DEF_LO_CORE_VID_SHIFT;
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/* Current value in amps */
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current_value_amps =
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(pstate_def.lo & PSTATE_DEF_LO_CUR_VAL_MASK) >> PSTATE_DEF_LO_CUR_VAL_SHIFT;
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/* Current divisor */
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current_divisor =
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(pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT;
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/* Voltage */
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if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) {
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/* Voltage off for VID codes 0xF8 to 0xFF */
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voltage_in_uvolts = 0;
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} else {
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voltage_in_uvolts =
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SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
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}
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/* Power in mW */
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power_in_mw = (voltage_in_uvolts) / 1000 * current_value_amps;
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switch (current_divisor) {
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case 0:
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break;
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case 1:
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power_in_mw = power_in_mw / 10L;
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break;
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case 2:
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power_in_mw = power_in_mw / 100L;
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break;
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case 3:
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/* current_divisor is set to an undefined value.*/
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printk(BIOS_WARNING, "Undefined current_divisor set for enabled P-state .\n");
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power_in_mw = 0;
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break;
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}
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return power_in_mw;
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}
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/*
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* Populate structure describing enabled p-states and return count of enabled p-states.
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*/
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static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
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struct acpi_xpss_sw_pstate *pstate_xpss_values)
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{
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msr_t pstate_def;
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size_t pstate_count, pstate;
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uint32_t pstate_enable, max_pstate;
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pstate_count = 0;
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max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
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for (pstate = 0; pstate <= max_pstate; pstate++) {
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pstate_def = rdmsr(PSTATE_0_MSR + pstate);
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pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
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>> PSTATE_DEF_HI_ENABLE_SHIFT;
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if (!pstate_enable)
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continue;
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pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
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pstate_values[pstate_count].power = get_pstate_core_power(pstate_def);
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pstate_values[pstate_count].transition_latency = 0;
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pstate_values[pstate_count].bus_master_latency = 0;
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pstate_values[pstate_count].control_value = pstate;
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pstate_values[pstate_count].status_value = pstate;
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pstate_xpss_values[pstate_count].core_freq =
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(uint64_t)pstate_values[pstate_count].core_freq;
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pstate_xpss_values[pstate_count].power =
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(uint64_t)pstate_values[pstate_count].power;
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pstate_xpss_values[pstate_count].transition_latency = 0;
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pstate_xpss_values[pstate_count].bus_master_latency = 0;
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pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
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pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
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pstate_count++;
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}
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return pstate_count;
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}
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void generate_cpu_entries(const struct device *device)
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{
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int cores, cpu;
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int logical_cores;
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size_t pstate_count, cpu, proc_blk_len;
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struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
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struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
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uint32_t threads_per_core, proc_blk_addr;
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uint32_t cstate_base_address =
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rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK;
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cores = get_cpu_count();
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printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
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const acpi_addr_t perf_ctrl = {
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = 64,
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.addrl = PS_CTL_REG,
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};
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const acpi_addr_t perf_sts = {
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = 64,
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.addrl = PS_STS_REG,
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};
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/* Generate BSP \_SB.P000 */
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acpigen_write_processor(0, ACPI_GPE0_BLK, 6);
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acpigen_pop_len();
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acpi_cstate_t cstate_info[] = {
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[0] = {
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.ctype = 1,
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.latency = 1,
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.power = 0,
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.resource = {
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = 2,
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.bit_offset = 2,
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.addrl = 0,
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.addrh = 0,
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},
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},
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[1] = {
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.ctype = 2,
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.latency = 400,
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.power = 0,
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.resource = {
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.space_id = ACPI_ADDRESS_SPACE_IO,
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.bit_width = 8,
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.bit_offset = 0,
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.addrl = cstate_base_address + 1,
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.addrh = 0,
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.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
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},
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},
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};
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threads_per_core = ((cpuid_ebx(CPUID_EBX_CORE_ID) & CPUID_EBX_THREADS_MASK)
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>> CPUID_EBX_THREADS_SHIFT)
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+ 1;
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pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
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logical_cores = get_cpu_count();
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for (cpu = 0; cpu < logical_cores; cpu++) {
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if (cpu == 0) {
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/* BSP values for \_SB.Pxxx */
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proc_blk_len = 6;
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proc_blk_addr = ACPI_GPE0_BLK;
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} else {
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/* AP values for \_SB.Pxxx */
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proc_blk_addr = 0;
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proc_blk_len = 0;
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}
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acpigen_write_processor(cpu, proc_blk_addr, proc_blk_len);
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acpigen_write_pct_package(&perf_ctrl, &perf_sts);
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acpigen_write_pss_object(pstate_values, pstate_count);
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acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
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if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
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acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
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HW_ALL);
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else
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acpigen_write_PSD_package(0, logical_cores, SW_ALL);
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acpigen_write_PPC(0);
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acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info));
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acpigen_write_CSD_package(cpu >> 1, threads_per_core, HW_ALL, 0);
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/* Generate AP \_SB.Pxxx */
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for (cpu = 1; cpu < cores; cpu++) {
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acpigen_write_processor(cpu, 0, 0);
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acpigen_pop_len();
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}
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}
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@ -500,7 +500,6 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current
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printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n");
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current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current);
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current = add_agesa_acpi_table(AMD_FSP_ACPI_CRAT_HOB_GUID, "CRAT", rsdp, current);
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current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current);
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28
src/soc/amd/picasso/include/soc/msr.h
Normal file
28
src/soc/amd/picasso/include/soc/msr.h
Normal file
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@ -0,0 +1,28 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file applies to AMD64 products.
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* The definitions come from the device's PPR.
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*/
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#ifndef SOC_AMD_PICASSO_MSR_H
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#define SOC_AMD_PICASSO_MSR_H
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/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
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#define PSTATE_DEF_HI_ENABLE_SHIFT 31
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#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT)
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#define PSTATE_DEF_LO_CUR_DIV_SHIFT 30
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#define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT)
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#define PSTATE_DEF_LO_CUR_VAL_SHIFT 22
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#define PSTATE_DEF_LO_CUR_VAL_MASK (0xFF << PSTATE_DEF_LO_CUR_VAL_SHIFT)
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#define PSTATE_DEF_LO_CORE_VID_SHIFT 14
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#define PSTATE_DEF_LO_CORE_VID_MASK (0xFF << PSTATE_DEF_LO_CORE_VID_SHIFT)
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#define PSTATE_DEF_LO_FREQ_DIV_SHIFT 8
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#define PSTATE_DEF_LO_FREQ_DIV_MASK (0x3F << PSTATE_DEF_LO_FREQ_DIV_SHIFT)
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#define PSTATE_DEF_LO_FREQ_DIV_MIN 0x8
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#define PSTATE_DEF_LO_EIGHTH_STEP_MAX 0x1A
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#define PSTATE_DEF_LO_FREQ_DIV_MAX 0x3E
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#define PSTATE_DEF_LO_FREQ_MUL_SHIFT 0
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#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
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#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
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#endif /* SOC_AMD_PICASSO_MSR_H */
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