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nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training 

Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a
did not take into account the default UI setting introduced in
change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM
instability and occassional failure to boot.

Use the correct 1UI value for the modified function semantics.

Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14073
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2016-03-12 17:17:23 -06:00
parent d43186418a
commit bc5ad1087b
1 changed files with 1 additions and 1 deletions
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2
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
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@ -1703,7 +1703,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
/* Reset the read data timing registers to 1UI before calculating MaxRdLatency */ /* Reset the read data timing registers to 1UI before calculating MaxRdLatency */
for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++) for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++)
current_read_dqs_delay[internal_lane] = 0x20 << 1; current_read_dqs_delay[internal_lane] = 0x20;
write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg);
/* Calculate and program MaxRdLatency */ /* Calculate and program MaxRdLatency */