From bc62834306e93198741c36c19ea2cda7e0537cc4 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Mon, 11 Jul 2016 21:26:11 -0700 Subject: [PATCH] intel/amenia: Add mainboard SMI handler This patch adds a mainboard SMI handler file which has functions to set proper Wake mask before going to sleep so that system can wake up on lidopen, key press etc. Also SCI mask is set on boot which will enable timely update of battery UI on charger connect/disconnect. BUG = chrome-os-partner:53992 TEST = Amenia platform wakes from S3 on lidopen, key press and also sysfs entry for AC is updated on charger connect/disconnect. Change-Id: If3dc6924c51c228241b7a647566b97398326ec0e Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/15616 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/amenia/Makefile.inc | 2 + src/mainboard/intel/amenia/smihandler.c | 70 +++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 src/mainboard/intel/amenia/smihandler.c diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc index 8d4d5f7058..3b6bca3c83 100644 --- a/src/mainboard/intel/amenia/Makefile.inc +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -6,3 +6,5 @@ ramstage-y += mainboard.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/amenia/smihandler.c b/src/mainboard/intel/amenia/smihandler.c new file mode 100644 index 0000000000..3b855f25a1 --- /dev/null +++ b/src/mainboard/intel/amenia/smihandler.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "ec.h" + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + return; + + switch (slp_typ) { + case 3: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + enable_gpe(GPIO_TIER_1_SCI); + break; + case 5: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); + break; + } + + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0) + ; +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + return 0; + + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + break; + case APM_CNT_ACPI_DISABLE: + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); + break; + } + return 0; +}