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mb/google/rex: Modify the PIN name as per schematics 

This patch updates the GPIO PIN name as per Proto 1 schematics dated
12/14/2022.

TEST=Not code change, just updated the comment section.

Change-Id: Ic076ab35689fd2afb7c18eff065a90b9464a6b1d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2022-12-14 14:52:31 +05:30
parent 4c9440c673
commit bc6a305f82
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/rex/variants/rex0/gpio.c
View File

@ -98,7 +98,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_C00, 0, DEEP),
/* GPP_C01 : [] ==> USI_RST_L */
PAD_CFG_GPO(GPP_C01, 0, DEEP),
/* GPP_C02 : GPP_C02_STRAP ==> Component NC */
/* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */
PAD_NC(GPP_C02, NONE),
/* GPP_C03 : [] ==> EN_WCAM_SENR_PWR */
PAD_CFG_GPO_LOCK(GPP_C03, 0, LOCK_CONFIG),
@ -106,7 +106,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO_LOCK(GPP_C04, 0, LOCK_CONFIG),
/* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */
PAD_CFG_GPO(GPP_C05, 1, PLTRST),
/* GPP_C06 : [] ==> USI_REPORT_EN */
/* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */
/*
* FIXME: Remove this code after resolving b/247029304.
*
@ -121,7 +121,7 @@ static const struct pad_config gpio_table[] = {
* `Report EN enabled (ramstage) -> POWER enabled (ACPI) -> RESET deasserted (ACPI)`
*/
PAD_CFG_GPO(GPP_C06, 1, DEEP),
/* GPP_C07 : [] ==> USI_INT */
/* GPP_C07 : [] ==> SOC_TCHSCR_INT */
PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE),
/* GPP_C08 : [] ==> SOCHOT_ODL */
PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2),