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Exynos5420: tighten up display port delays 

Shorten a few delays, and make some delays shorter but let the
loops have a higher termination count (i.e. give it the same
amount of time to warm up, but check more frequently).

Change-Id: Id9fe846ae3a8d792b14d62aea4e98d8aad05be43
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66156
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit a112e77f2f21f41f982ca22bebdac213cc8d233a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6506
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Ronald G. Minnich 2013-08-16 19:53:41 -07:00 committed by Isaac Christensen
parent f2c4241b81
commit bc6cc112e2
2 changed files with 3 additions and 3 deletions
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2
src/cpu/samsung/exynos5420/dp.h
View File

@ -1187,7 +1187,7 @@ static inline u32 exynos_fimd_get_base_offset(void)
#define EXYNOS_DP_CLK_ENABLE (1 << 1) #define EXYNOS_DP_CLK_ENABLE (1 << 1)
#define EXYNOS_MIE_CLK_ENABLE (3 << 0) #define EXYNOS_MIE_CLK_ENABLE (3 << 0)
#define DP_TIMEOUT_LOOP_COUNT 100 #define DP_TIMEOUT_LOOP_COUNT 1000
#define MAX_CR_LOOP 5 #define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 4 #define MAX_EQ_LOOP 4

4
src/cpu/samsung/exynos5420/dp_lowlevel.c
View File

@ -452,7 +452,7 @@ unsigned int exynos_dp_detect_hpd(void)
while (exynos_dp_get_plug_in_status() != 0) { while (exynos_dp_get_plug_in_status() != 0) {
if (timeout_loop == 0) if (timeout_loop == 0)
return -1; return -1;
mdelay(10); mdelay(1);
timeout_loop--; timeout_loop--;
} }
@ -865,7 +865,7 @@ void exynos_dp_reset_macro(void)
lwrite32(reg, &dp_regs->phy_test); lwrite32(reg, &dp_regs->phy_test);
/* 10 us is the minimum Macro reset time. */ /* 10 us is the minimum Macro reset time. */
mdelay(1); udelay(50);
reg &= ~MACRO_RST; reg &= ~MACRO_RST;
lwrite32(reg, &dp_regs->phy_test); lwrite32(reg, &dp_regs->phy_test);