From bc749a068ad8640497abb1985f0ccfdd66cd5ffb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 7 Apr 2022 15:10:35 +0200 Subject: [PATCH] soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some Super I/Os may be strapped to respond on the secondary ports 0x4e/0x4f. Enable them early so that mainboard is able to initialize a serial port for example. Signed-off-by: Michał Żygowski Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63461 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/bootblock/pch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 60f3a851b7..bd204cdb64 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -103,8 +103,8 @@ static void soc_config_acpibase(void) void pch_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F | + LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO))