GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cpu/intel/car/p4-netburst: Prepare for x86_64 

Use proper car symbols.

Change-Id: I169fd6020e5b81da66dbe4fe83ba446eedc882e9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2021-07-02 10:03:17 +02:00 committed by Patrick Georgi
parent 3476410039
commit bc7b63fa6b
2 changed files with 11 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/intel/car/cache_as_ram_symbols.inc
View File

@ -18,3 +18,6 @@ car_mtrr_mask:
car_mtrr_start: car_mtrr_start:
.uintptr_t _car_mtrr_start .uintptr_t _car_mtrr_start
xip_mtrr_mask:
.uintptr_t _xip_mtrr_mask

14
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@ -11,6 +11,8 @@
.section .init .section .init
.global bootblock_pre_c_entry .global bootblock_pre_c_entry
#include <cpu/intel/car/cache_as_ram_symbols.inc>
.code32 .code32
_cache_as_ram_setup: _cache_as_ram_setup:
@ -212,7 +214,7 @@ sipi_complete:
/* Set Cache-as-RAM base address. */ /* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx movl $(MTRR_PHYS_BASE(0)), %ecx
movl $_car_mtrr_start, %eax movl car_mtrr_start, %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
@ -220,7 +222,7 @@ sipi_complete:
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr rdmsr
movl $_car_mtrr_mask, %eax movl car_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
@ -272,12 +274,12 @@ no_msr_11e:
/* Cache the whole rom to fetch microcode updates */ /* Cache the whole rom to fetch microcode updates */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $_rom_mtrr_base, %eax movl rom_mtrr_base, %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $_rom_mtrr_mask, %eax movl rom_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
@ -324,12 +326,12 @@ cache_rom:
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $_program, %eax movl $_program, %eax
andl $_xip_mtrr_mask, %eax andl xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $_xip_mtrr_mask, %eax movl xip_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr