This patch adds support for the AMD Geode LX CPU. (rediffed)
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
Stefan Reinauer
parent
5941c25fe8
commit
bc8176c552
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@ -0,0 +1,370 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
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#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
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#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
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#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
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#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
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#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
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#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
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#include <cpu/amd/lxdef.h>
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/***************************************************************************
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/**
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/** DCacheSetup
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/**
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/** Setup data cache for use as RAM for a stack.
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/**
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/***************************************************************************/
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DCacheSetup:
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invd
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/* set cache properties */
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movl $CPU_RCONF_DEFAULT, %ecx
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rdmsr
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movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */
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wrmsr
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/* in LX DCDIS is set after POR which disables the cache..., clear this bit */
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movl CPU_DM_CONFIG0,%ecx
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rdmsr
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andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */
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wrmsr
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/* get cache timing params from BIOS config data locations and apply */
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/* fix delay controls for DM and IM arrays */
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/* fix delay controls for DM and IM arrays */
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movl $CPU_BC_MSS_ARRAY_CTL0, %ecx
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xorl %edx, %edx
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movl $0x2814D352, %eax
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wrmsr
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movl $CPU_BC_MSS_ARRAY_CTL1, %ecx
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xorl %edx, %edx
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movl $0x1068334D, %eax
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wrmsr
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movl $CPU_BC_MSS_ARRAY_CTL2, %ecx
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movl $0x00000106, %edx
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movl $0x83104104, %eax
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wrmsr
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movl $GLCP_FIFOCTL, %ecx
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rdmsr
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movl $0x00000005, %edx
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wrmsr
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/* Enable setting */
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movl $CPU_BC_MSS_ARRAY_CTL_ENA, %ecx
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xorl %edx, %edx
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movl $0x01, %eax
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wrmsr
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/* Get cleaned up. */
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xorl %edi, %edi
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xorl %esi, %esi
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xorl %ebp, %ebp
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/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */
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/* remember, there is NO stack yet... */
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/* Tell cache we want to fill WAY 0 starting at the top */
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xorl %edx, %edx
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xorl %eax, %eax
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movl $CPU_DC_INDEX, %ecx
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wrmsr
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/* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
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movl $LX_STACK_BASE, %ebp /* init to start address */
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orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
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/* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
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movl $LX_NUM_CACHELINES, %edi
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DCacheSetupFillWay:
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/* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
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/* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
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movw $0x04, %si
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xorl %edx, %edx
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xorl %eax, %eax
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movl $CPU_DC_DATA, %ecx
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DCacheSetup_quadWordLoop:
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wrmsr
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decw %si
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jnz DCacheSetup_quadWordLoop
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/* Set the tag for this line, need to do this for every new cache line to validate it! */
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/* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
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xorl %edx, %edx
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movl %ebp, %eax
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movl $CPU_DC_TAG, %ecx
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wrmsr
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/* switch to next line */
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/* lines are in Bits10:4 */
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/* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */
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movl $CPU_DC_INDEX, %ecx
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rdmsr
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addl $0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */
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wrmsr
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decl %edi
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jnz DCacheSetupFillWay
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/* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */
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addl $LX_CACHEWAY_SIZE, %ebp
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cmpl $LX_STACK_END, %ebp
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jge leave_DCacheSetup
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movl $LX_NUM_CACHELINES, %edi
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/* switch to next way */
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movl $CPU_DC_INDEX, %ecx
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rdmsr
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addl $0x01, %eax
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andl $0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */
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wrmsr
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jmp DCacheSetupFillWay
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leave_DCacheSetup:
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xorl %edi, %edi
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xorl %esi, %esi
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xorl %ebp, %ebp
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/* Disable the cache, but ... DO NOT INVALIDATE the tags. */
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/* Memory reads and writes will all hit in the cache. */
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/* Cache updates and memory write-backs will not occur ! */
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movl %cr0, %eax
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orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */
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movl %eax, %cr0
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/* Now point sp to the cached stack. */
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/* The stack will be fully functional at this location. No system memory is required at all ! */
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/* set up the stack pointer */
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movl $LX_STACK_END, %eax
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movl %eax, %esp
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/* test the stack*/
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movl $0x0F0F05A5A, %edx
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pushl %edx
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popl %ecx
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cmpl %ecx, %edx
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je DCacheSetupGood
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movb $0xC5, %al
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outb %al, $0x80
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DCacheSetupBad:
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hlt /* issues */
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jmp DCacheSetupBad
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DCacheSetupGood:
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/* Go do early init and memory setup */
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call cache_as_ram_main
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/* If you wanted to maintain the stack in memory you would need to set the tags as dirty
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so the wbinvd would push out the old stack contents to memory */
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/* Clear the cache, the following code from crt0.S.lb will setup a new stack*/
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wbinvd
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/* the following code is from crt0.S.lb */
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/* This takes the place of the post-CAR funtions that the K8 uses to setup the stack and copy LB low.*/
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#ifndef CONSOLE_DEBUG_TX_STRING
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/* uses: esp, ebx, ax, dx */
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# define __CRT_CONSOLE_TX_STRING(string) \
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mov string, %ebx ; \
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CALLSP(crt_console_tx_string)
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# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
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# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
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# else
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# define CONSOLE_DEBUG_TX_STRING(string)
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# endif
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#endif
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
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/*
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* Copy data into RAM and clear the BSS. Since these segments
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* isn\'t really that big we just copy/clear using bytes, not
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* double words.
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*/
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intel_chip_post_macro(0x11) /* post 11 */
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cld /* clear direction flag */
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/* copy linuxBIOS from it's initial load location to
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* the location it is compiled to run at.
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* Normally this is copying from FLASH ROM to RAM.
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*/
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#if !CONFIG_COMPRESS
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movl $_liseg, %esi
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movl $_iseg, %edi
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movl $_eiseg, %ecx
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subl %edi, %ecx
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rep movsb
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#else
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leal 4+_liseg, %esi
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leal _iseg, %edi
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movl %ebp, %esp /* preserve %ebp */
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movl $-1, %ebp /* last_m_off = -1 */
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jmp dcl1_n2b
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/* ------------- DECOMPRESSION -------------
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Input:
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%esi - source
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%edi - dest
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%ebp - -1
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cld
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Output:
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%eax - 0
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%ecx - 0
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*/
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.macro getbit bits
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.if \bits == 1
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addl %ebx, %ebx
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jnz 1f
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.endif
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movl (%esi), %ebx
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subl $-4, %esi /* sets carry flag */
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adcl %ebx, %ebx
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1:
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.endm
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decompr_literals_n2b:
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movsb
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decompr_loop_n2b:
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addl %ebx, %ebx
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jnz dcl2_n2b
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dcl1_n2b:
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getbit 32
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dcl2_n2b:
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jc decompr_literals_n2b
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xorl %eax, %eax
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incl %eax /* m_off = 1 */
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loop1_n2b:
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getbit 1
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adcl %eax, %eax /* m_off = m_off*2 + getbit() */
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getbit 1
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jnc loop1_n2b /* while(!getbit()) */
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xorl %ecx, %ecx
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subl $3, %eax
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jb decompr_ebpeax_n2b /* if (m_off == 2) goto decompr_ebpeax_n2b ? */
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shll $8, %eax
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movb (%esi), %al /* m_off = (m_off - 3)*256 + src[ilen++] */
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incl %esi
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xorl $-1, %eax
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jz decompr_end_n2b /* if (m_off == 0xffffffff) goto decomp_end_n2b */
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movl %eax, %ebp /* last_m_off = m_off ?*/
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decompr_ebpeax_n2b:
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getbit 1
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adcl %ecx, %ecx /* m_len = getbit() */
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getbit 1
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adcl %ecx, %ecx /* m_len = m_len*2 + getbit()) */
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jnz decompr_got_mlen_n2b /* if (m_len == 0) goto decompr_got_mlen_n2b */
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incl %ecx /* m_len++ */
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loop2_n2b:
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getbit 1
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adcl %ecx, %ecx /* m_len = m_len*2 + getbit() */
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getbit 1
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jnc loop2_n2b /* while(!getbit()) */
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incl %ecx
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incl %ecx /* m_len += 2 */
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decompr_got_mlen_n2b:
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cmpl $-0xd00, %ebp
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adcl $1, %ecx /* m_len = m_len + 1 + (last_m_off > 0xd00) */
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movl %esi, %edx
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leal (%edi,%ebp), %esi /* m_pos = dst + olen + -m_off */
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rep
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movsb /* dst[olen++] = *m_pos++ while(m_len > 0) */
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movl %edx, %esi
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jmp decompr_loop_n2b
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decompr_end_n2b:
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intel_chip_post_macro(0x12) /* post 12 */
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movl %esp, %ebp
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#endif
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CONSOLE_DEBUG_TX_STRING($str_pre_main)
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leal _iseg, %edi
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jmp *%edi
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.Lhlt:
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intel_chip_post_macro(0xee) /* post fail ee */
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hlt
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jmp .Lhlt
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#ifdef __CRT_CONSOLE_TX_STRING
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/* Uses esp, ebx, ax, dx */
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crt_console_tx_string:
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mov (%ebx), %al
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inc %ebx
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cmp $0, %al
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jne 9f
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RETSP
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9:
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/* Base Address */
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#ifndef TTYS0_BASE
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#define TTYS0_BASE 0x3f8
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#endif
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/* Data */
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#define TTYS0_RBR (TTYS0_BASE+0x00)
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/* Control */
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#define TTYS0_TBR TTYS0_RBR
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#define TTYS0_IER (TTYS0_BASE+0x01)
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#define TTYS0_IIR (TTYS0_BASE+0x02)
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#define TTYS0_FCR TTYS0_IIR
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#define TTYS0_LCR (TTYS0_BASE+0x03)
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#define TTYS0_MCR (TTYS0_BASE+0x04)
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#define TTYS0_DLL TTYS0_RBR
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#define TTYS0_DLM TTYS0_IER
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/* Status */
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#define TTYS0_LSR (TTYS0_BASE+0x05)
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#define TTYS0_MSR (TTYS0_BASE+0x06)
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#define TTYS0_SCR (TTYS0_BASE+0x07)
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mov %al, %ah
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10: mov $TTYS0_LSR, %dx
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inb %dx, %al
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test $0x20, %al
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je 10b
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mov $TTYS0_TBR, %dx
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mov %ah, %al
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outb %al, %dx
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jmp crt_console_tx_string
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#endif /* __CRT_CONSOLE_TX_STRING */
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#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
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.section ".rom.data"
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str_copying_to_ram: .string "Copying LinuxBIOS to ram.\r\n"
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str_pre_main: .string "Jumping to LinuxBIOS.\r\n"
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.previous
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#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
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@ -24,35 +24,13 @@
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include <cpu/amd/lxdef.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/amd/lxdef.h>
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#if 0
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void
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bug645(void){
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msr_t msr;
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rdmsr(CPU_ID_CONFIG);
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msr.whatever |= ID_CONFIG_SERIAL_SET;
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wrmsr(msr);
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}
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void
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bug573(void){
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msr_t msr;
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msr = rdmsr(MC_GLD_MSR_PM);
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msr.eax &= 0xfff3;
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wrmsr(MC_GLD_MSR_PM);
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}
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#endif
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/**************************************************************************
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*
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* pcideadlock
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@ -61,14 +39,8 @@ bug573(void){
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* PCI cache deadlock
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* There is also fix code in cache and PCI functions. This bug is very is pervasive.
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*
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* Entry:
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* Exit:
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* Modified:
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*
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**************************************************************************/
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static void
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pcideadlock(void)
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{
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static void pcideadlock(void){
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msr_t msr;
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/*
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@ -77,18 +49,9 @@ pcideadlock(void)
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* for PCI writes to complete.
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*/
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msr = rdmsr(CPU_DM_CONFIG0);
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msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
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msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
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msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
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wrmsr(CPU_DM_CONFIG0, msr);
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/* interlock instruction fetches to WS regions with data accesses.
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* This prevents an instruction fetch from going out to PCI if the
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* data side is about to make a request.
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*/
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msr = rdmsr(CPU_IM_CONFIG);
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msr.lo |= IM_CONFIG_LOWER_QWT_SET;
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wrmsr(CPU_IM_CONFIG, msr);
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/* write serialize memory hole to PCI. Need to unWS when something is
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* shadowed regardless of cachablility.
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@ -100,249 +63,6 @@ pcideadlock(void)
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wrmsr( CPU_RCONF_E0_FF, msr);
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}
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/****************************************************************************
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*
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* CPUbug784
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*
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* Bugtool #784 + #792
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*
|
||||
* Fix CPUID instructions for < 3.0 CPUs
|
||||
*
|
||||
* Entry:
|
||||
* Exit:
|
||||
* Modified:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void bug784(void)
|
||||
{
|
||||
msr_t msr;
|
||||
//static char *name = "Geode by NSC";
|
||||
|
||||
/* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
|
||||
* would do this -- the OS can figure this type of stuff out!
|
||||
*/
|
||||
msr = rdmsr(0x3006);
|
||||
msr.hi = 0x646f6547;
|
||||
wrmsr(0x3006, msr);
|
||||
|
||||
msr = rdmsr(0x3007);
|
||||
msr.hi = 0x79622065;
|
||||
msr.lo = 0x43534e20;
|
||||
wrmsr(0x3007, msr);
|
||||
|
||||
msr = rdmsr(0x3002);
|
||||
wrmsr(0x3008, msr);
|
||||
|
||||
/* More CPUID to match AMD better. #792*/
|
||||
msr = rdmsr(0x3009);
|
||||
msr.hi = 0x0C0C0A13D;
|
||||
msr.lo = 0x00000000;
|
||||
wrmsr(0x3009, msr);
|
||||
}
|
||||
|
||||
/* cpubug 1398: enable MC if we KNOW we have DDR*/
|
||||
/**************************************************************************
|
||||
*
|
||||
* CPUbugIAENG1398
|
||||
*
|
||||
* ClearQuest #IAENG1398
|
||||
* The MC can not be enabled with SDR memory but can for DDR. Enable for
|
||||
* DDR here if the setup token is "Default"
|
||||
* Add this back to core by default once 2.0 CPUs are not supported.
|
||||
* Entry:
|
||||
* Exit:
|
||||
* Modified:
|
||||
*
|
||||
**************************************************************************/
|
||||
void eng1398(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr = rdmsr(MSR_GLCP+0x17);
|
||||
if ((msr.lo & 0xff) <= CPU_REV_2_0) {
|
||||
msr = rdmsr(GLCP_SYS_RSTPLL);
|
||||
if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
|
||||
return;
|
||||
}
|
||||
|
||||
/* no CMOS/NVRAM to check, so enable MC Clock Gating */
|
||||
msr = rdmsr(MC_GLD_MSR_PM);
|
||||
msr.lo |= 3; /* enable MC clock gating.*/
|
||||
wrmsr(MC_GLD_MSR_PM, msr);
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
*
|
||||
* CPUbugIAENG2900
|
||||
*
|
||||
* Clear Quest IAENG00002900, VSS 118.150
|
||||
*
|
||||
* BTB issue causes blue screen in windows, but the fix is required
|
||||
* for all operating systems.
|
||||
*
|
||||
* Entry:
|
||||
* Exit:
|
||||
* Modified:
|
||||
*
|
||||
**************************************************************************/
|
||||
void
|
||||
eng2900(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
printk_debug("CPU_BUG:%s\n", __FUNCTION__);
|
||||
/* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
|
||||
msr = rdmsr(0x3003);
|
||||
msr.hi &= 0xFFFFF7FF;
|
||||
wrmsr(0x3003, msr);
|
||||
|
||||
/* change this value to zero if you need to disable this BTB SWAPSiF. */
|
||||
if (1) {
|
||||
|
||||
/* Disable enable_actions in DIAGCTL while setting up GLCP */
|
||||
msr.hi = 0;
|
||||
msr.lo = 0;
|
||||
wrmsr(MSR_GLCP + 0x005f, msr);
|
||||
|
||||
/* Changing DBGCLKCTL register to GeodeLink */
|
||||
msr.hi = 0;
|
||||
msr.lo = 0;
|
||||
wrmsr(MSR_GLCP + 0x0016, msr);
|
||||
|
||||
msr.hi = 0;
|
||||
msr.lo = 2;
|
||||
wrmsr(MSR_GLCP + 0x0016, msr);
|
||||
|
||||
/* The code below sets up the CPU to stall for 4 GeodeLink
|
||||
* clocks when CPU is snooped. Because setting XSTATE to 0
|
||||
* overrides any other XSTATE action, the code will always
|
||||
* stall for 4 GeodeLink clocks after a snoop request goes
|
||||
* away even if it occured a clock or two later than a
|
||||
* different snoop; the stall signal will never 'glitch high'
|
||||
* for only one or two CPU clocks with this code.
|
||||
*/
|
||||
|
||||
/* Send mb0 port 3 requests to upper GeodeLink diag bits
|
||||
[63:32] */
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x80338041;
|
||||
wrmsr(MSR_GLIU0 + 0x2005, msr);
|
||||
|
||||
/* set5m watches request ready from mb0 to CPU (snoop) */
|
||||
msr.hi = 0x5ad68000;
|
||||
msr.lo = 0;
|
||||
wrmsr(MSR_GLCP + 0x0045, msr);
|
||||
|
||||
/* SET4M will be high when state is idle (XSTATE=11) */
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x0140;
|
||||
wrmsr(MSR_GLCP + 0x0044, msr);
|
||||
|
||||
/* SET5n to watch for processor stalled state */
|
||||
msr.hi = 0x2000;
|
||||
msr.lo = 0;
|
||||
wrmsr(MSR_GLCP + 0x004D, msr);
|
||||
|
||||
/* Writing action number 13: XSTATE=0 to occur when CPU is
|
||||
snooped unless we're stalled */
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x00400000;
|
||||
wrmsr(MSR_GLCP + 0x0075, msr);
|
||||
|
||||
/* Writing action number 11: inc XSTATE every GeodeLink clock
|
||||
unless we're idle */
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x30000;
|
||||
wrmsr(MSR_GLCP + 0x0073, msr);
|
||||
|
||||
/* Writing action number 5: STALL_CPU_PIPE when exitting idle
|
||||
state or not in idle state */
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x00430000;
|
||||
wrmsr(MSR_GLCP + 0x006D, msr);
|
||||
|
||||
/* Writing DIAGCTL Register to enable the stall action and to
|
||||
let set5m watch the upper GeodeLink diag bits. */
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x80004000;
|
||||
wrmsr(MSR_GLCP + 0x005f, msr);
|
||||
}
|
||||
}
|
||||
|
||||
void bug118253(void)
|
||||
{
|
||||
/* GLPCI PIO Post Control shouldn't be enabled */
|
||||
msr_t msr;
|
||||
|
||||
msr = rdmsr(GLPCI_SPARE);
|
||||
msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
|
||||
wrmsr(GLPCI_SPARE, msr);
|
||||
}
|
||||
|
||||
void bug118339(void)
|
||||
{
|
||||
/* per AMD, do this always */
|
||||
msr_t msr = {0,0};
|
||||
int msrnum;
|
||||
|
||||
/* Disable enable_actions in DIAGCTL while setting up GLCP */
|
||||
wrmsr(MSR_GLCP + 0x005f, msr);
|
||||
|
||||
/* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
|
||||
msrnum = MSR_GLCP + 0x042;
|
||||
/* msr.hi = 2d6b8000h */;
|
||||
msr.hi = 0x596b8000;
|
||||
msr.lo = 0x00000a00;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* SET3M fires if MBUS changed and VG pri is odd */
|
||||
msrnum = MSR_GLCP + 0x043;
|
||||
msr.hi = 0x596b8040;
|
||||
msr.lo = 0;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Put VG request data on lower diag bus */
|
||||
msrnum = MSR_GLIU0 + 0x2005;
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x80338041;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Increment Y state if SET3M if true */
|
||||
msrnum = MSR_GLCP + 0x074;
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x0000c000;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set up MBUS action to PRI=3 read of MBIU */
|
||||
msrnum = MSR_GLCP + 0x020;
|
||||
msr.hi = 0x0000d863;
|
||||
msr.lo = 0x20002000;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
|
||||
msrnum = MSR_GLCP + 0x071;
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x00000c00;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Writing DIAGCTL */
|
||||
msrnum = MSR_GLCP + 0x005f;
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x80004000;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
|
||||
/* As per Todd Roberts in PBz1094 and PBz1095 */
|
||||
/* Moved from CPUREG to CPUBUG per Tom Sylla */
|
||||
msrnum = 0x04C000042; /* GLCP SETMCTL Register */;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi |= 8; /* Bit 35 = MCP_IN */
|
||||
wrmsr(msrnum, msr);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/***/
|
||||
/** DisableMemoryReorder*/
|
||||
|
|
@ -353,62 +73,18 @@ void bug118339(void)
|
|||
/** This is safe to do here and not in MC init since there is nothing*/
|
||||
/** to maintain coherency with and the cache is not enabled yet.*/
|
||||
/***/
|
||||
/***/
|
||||
/** Entry:*/
|
||||
/** Exit:*/
|
||||
/** Modified:*/
|
||||
/***/
|
||||
/****************************************************************************/
|
||||
void disablememoryreadorder(void)
|
||||
{
|
||||
static void disablememoryreadorder(void){
|
||||
msr_t msr;
|
||||
msr = rdmsr(MC_CF8F_DATA);
|
||||
|
||||
msr = rdmsr(MC_CF8F_DATA);
|
||||
msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
|
||||
wrmsr(MC_CF8F_DATA, msr);
|
||||
}
|
||||
|
||||
void
|
||||
cpubug(void)
|
||||
{
|
||||
#if 0 //GX3: any CPU bugs to fix here? :)
|
||||
msr_t msr;
|
||||
int rev;
|
||||
|
||||
msr = rdmsr(GLCP_CHIP_REVID);
|
||||
|
||||
rev = msr.lo & 0xff;
|
||||
if (rev < 0x20) {
|
||||
printk_err("%s: rev < 0x20! bailing!\n");
|
||||
return;
|
||||
}
|
||||
printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
|
||||
switch(rev)
|
||||
{
|
||||
case 0x20:
|
||||
/* For cpu version C3. Should be the only released version */
|
||||
void cpubug(void) {
|
||||
pcideadlock();
|
||||
eng1398();
|
||||
/* cs 5530 bug; ignore
|
||||
bug752();
|
||||
*/
|
||||
break;
|
||||
case 0x21:
|
||||
pcideadlock();
|
||||
eng1398();
|
||||
eng2900();
|
||||
bug118339();
|
||||
break;
|
||||
case 0x22:
|
||||
case 0x30:
|
||||
break;
|
||||
default:
|
||||
printk_err("unknown rev %x, bailing\n", rev);
|
||||
return;
|
||||
}
|
||||
bug784();
|
||||
bug118253();
|
||||
disablememoryreadorder();
|
||||
printk_debug("Done cpubug fixes \n");
|
||||
#endif
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,77 +20,219 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* ***************************************************************************/
|
||||
/* **/
|
||||
/* * BIST */
|
||||
/* **/
|
||||
/* * GX2 BISTs need to be run before BTB or caches are enabled.*/
|
||||
/* * BIST result left in registers on failure to be checked with FS2.*/
|
||||
/* **/
|
||||
/* ***************************************************************************/
|
||||
static void
|
||||
BIST(void){
|
||||
int msrnum;
|
||||
/**************************************************************************
|
||||
;*
|
||||
;* SetDelayControl
|
||||
;*
|
||||
;*************************************************************************/
|
||||
void SetDelayControl(void){
|
||||
unsigned int msrnum, glspeed;
|
||||
unsigned char spdbyte0, spdbyte1;
|
||||
msr_t msr;
|
||||
|
||||
/* DM*/
|
||||
msrnum = CPU_DM_CONFIG0;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
|
||||
glspeed = GeodeLinkSpeed();
|
||||
|
||||
/* fix delay controls for DM and IM arrays */
|
||||
msrnum = CPU_BC_MSS_ARRAY_CTL0;
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x2814D352;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
msr.lo = 0x00000003F;
|
||||
msr.hi = 0x000000000;
|
||||
msrnum = CPU_DM_BIST;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
|
||||
msr = rdmsr(msrnum); /* read back for pass fail*/
|
||||
msr.lo &= 0x0F3FF0000;
|
||||
if (msr.lo != 0xfeff0000)
|
||||
goto BISTFail;
|
||||
|
||||
msrnum = CPU_DM_CONFIG0;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* FPU*/
|
||||
msr.lo = 0x000000131;
|
||||
msrnum = CPU_BC_MSS_ARRAY_CTL1;
|
||||
msr.hi = 0;
|
||||
msrnum = CPU_FP_UROM_BIST;
|
||||
msr.lo = 0x1068334D;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
|
||||
inb(0x80); /* IO delay*/
|
||||
msr = rdmsr(msrnum); /* read back for pass fail*/
|
||||
while ((msr.lo&0x884) != 0x884)
|
||||
msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
|
||||
if ((msr.lo&0x642) != 0x642)
|
||||
goto BISTFail;
|
||||
msrnum = CPU_BC_MSS_ARRAY_CTL2;
|
||||
msr.hi = 0x00000106;
|
||||
msr.lo = 0x83104104;
|
||||
wrmsr(msrnum,msr);
|
||||
|
||||
msrnum = GLCP_FIFOCTL;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi = 0x00000005;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
|
||||
msrnum = CPU_FP_UROM_BIST;
|
||||
/* Enable setting */
|
||||
msrnum = CPU_BC_MSS_ARRAY_CTL_ENA;
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x00000001;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
|
||||
/* BTB*/
|
||||
msr.lo = 0x000000303;
|
||||
msr.hi = 0x000000000;
|
||||
msrnum = CPU_PF_BTBRMA_BIST;
|
||||
wrmsr(msrnum, msr);
|
||||
/* Debug Delay Control Setup Check
|
||||
Leave it alone if it has been setup. FS2 or something is here.*/
|
||||
msrnum = GLCP_DELAY_CONTROLS;
|
||||
msr = rdmsr(msrnum);
|
||||
if (msr.lo & ~(0x7C0)){
|
||||
return;
|
||||
}
|
||||
|
||||
outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/
|
||||
msr = rdmsr(msrnum); /* read back for pass fail*/
|
||||
if ((msr.lo & 0x3030) != 0x3030)
|
||||
goto BISTFail;
|
||||
|
||||
/*
|
||||
; Delay Controls based on DIMM loading. UGH!
|
||||
; # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
|
||||
; Note - We only support module width of 64.
|
||||
*/
|
||||
spdbyte0 = spd_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
|
||||
if (spdbyte0 !=0xFF){
|
||||
spdbyte0 = (unsigned char) 64/spdbyte0 * (unsigned char) (spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS));
|
||||
}
|
||||
else{
|
||||
spdbyte0=0;
|
||||
}
|
||||
|
||||
spdbyte1 = spd_read_byte(DIMM1, SPD_PRIMARY_SDRAM_WIDTH);
|
||||
if (spdbyte1 !=0xFF){
|
||||
spdbyte1 = (unsigned char) 64/spdbyte1 * (unsigned char) (spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS));
|
||||
}
|
||||
else{
|
||||
spdbyte1=0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* The current thinking. Subject to change...
|
||||
|
||||
; "FUTURE ROBUSTNESS" PROPOSAL
|
||||
; ----------------------------
|
||||
; DIMM Max MBUS MC 0x2000001A bits 26:24
|
||||
;DIMMs devices Frequency MCP 0x4C00000F Setting vvv
|
||||
;----- ------- --------- ---------------------- ----------
|
||||
;1 4 400MHz 0x82*100FF 0x56960004 4
|
||||
;1 8 400MHz 0x82*100AA 0x56960004 4
|
||||
;1 16 400MHz 0x82*10055 0x56960004 4
|
||||
;
|
||||
;2 4,4 400MHz 0x82710000 0x56960004 4
|
||||
;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
|
||||
;
|
||||
;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
|
||||
;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
|
||||
;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
|
||||
;
|
||||
;1 4 <=333MHz 0x83*100FF 0x56960004 3
|
||||
;1 8 <=333MHz 0x83*100AA 0x56960004 3
|
||||
;1 16 <=333MHz 0x83*100AA 0x56960004 3
|
||||
;
|
||||
;2 4,4 <=333MHz 0x837100A5 0x56960004 3
|
||||
;2 8,8 <=333MHz 0x937100A5 0x56960004 3
|
||||
;
|
||||
;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
|
||||
;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
|
||||
;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
|
||||
;=========================================================================
|
||||
;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
|
||||
; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
|
||||
; Bits 54:52 should always be set to '111'.
|
||||
|
||||
;No VTT termination
|
||||
;-------------------------------------
|
||||
;ADDR/CTL have 22 ohm series R
|
||||
;DQ/DQM/DQS have 33 ohm series R
|
||||
;
|
||||
; DIMM Max MBUS
|
||||
;DIMMs devices Frequency MCP 0x4C00000F Setting
|
||||
;----- ------- --------- ----------------------
|
||||
;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa.
|
||||
;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change,
|
||||
;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side.
|
||||
;1 8 <=333MHz 0xF2F100FF 0x56960004 3
|
||||
;1 16 <=333MHz 0xF2F100FF 0x56960004 3
|
||||
*/
|
||||
msr.hi = msr.lo = 0;
|
||||
|
||||
if (spdbyte0 == 0 || spdbyte1 == 0){
|
||||
/* one dimm solution */
|
||||
if (spdbyte1 == 0){
|
||||
msr.hi |= 0x000800000;
|
||||
}
|
||||
spdbyte0 += spdbyte1;
|
||||
if (spdbyte0 > 8){
|
||||
/* large dimm */
|
||||
if (glspeed < 334){
|
||||
msr.hi |= 0x0837100AA;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
else{
|
||||
msr.hi |= 0x082710055;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
}
|
||||
else if (spdbyte0 > 4){
|
||||
/* medium dimm */
|
||||
if (glspeed < 334){
|
||||
msr.hi |= 0x0837100AA;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
else{
|
||||
msr.hi |= 0x0827100AA;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
}
|
||||
else{
|
||||
/* small dimm */
|
||||
if (glspeed < 334){
|
||||
msr.hi |= 0x0837100FF;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
else{
|
||||
msr.hi |= 0x0827100FF;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
}
|
||||
}
|
||||
else{
|
||||
/* two dimm solution */
|
||||
spdbyte0 += spdbyte1;
|
||||
if (spdbyte0 > 24){
|
||||
/* huge dimms */
|
||||
if (glspeed < 334){
|
||||
msr.hi |= 0x0B37100A5;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
else{
|
||||
msr.hi |= 0x0B2710000;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
}
|
||||
else if (spdbyte0 > 16){
|
||||
/* large dimms */
|
||||
if (glspeed < 334){
|
||||
msr.hi |= 0x0B37100A5;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
else{
|
||||
msr.hi |= 0x0B27100A5;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
}
|
||||
else if (spdbyte0 >= 8){
|
||||
/* medium dimms */
|
||||
if (glspeed < 334){
|
||||
msr.hi |= 0x0937100A5;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
else{
|
||||
msr.hi |= 0x0C27100A5;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
}
|
||||
else{
|
||||
/* small dimms */
|
||||
if (glspeed < 334){
|
||||
msr.hi |= 0x0837100A5;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
else{
|
||||
msr.hi |= 0x082710000;
|
||||
msr.lo |= 0x056960004;
|
||||
}
|
||||
}
|
||||
}
|
||||
wrmsr(GLCP_DELAY_CONTROLS,msr);
|
||||
return;
|
||||
|
||||
BISTFail:
|
||||
print_err("BIST failed!\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
/* ***************************************************************************/
|
||||
/* * cpuRegInit*/
|
||||
/* ***************************************************************************/
|
||||
|
|
@ -99,173 +241,78 @@ cpuRegInit (void){
|
|||
int msrnum;
|
||||
msr_t msr;
|
||||
|
||||
//GX3 suspend: what is desired?
|
||||
|
||||
/* Enable Suspend on Halt*/
|
||||
/*msrnum = CPU_XC_CONFIG;
|
||||
/* Castle 2.0 BTM periodic sync period. */
|
||||
/* [40:37] 1 sync record per 256 bytes */
|
||||
msrnum = CPU_PF_CONF;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= XC_CONFIG_SUSP_ON_HLT;
|
||||
wrmsr(msrnum, msr);*/
|
||||
|
||||
/* ENable SUSP and allow TSC to run in Suspend */
|
||||
/* to keep speed detection happy*/
|
||||
/*msrnum = CPU_BC_CONF_0;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
|
||||
wrmsr(msrnum, msr);*/
|
||||
|
||||
/* Setup throttling to proper mode if it is ever enabled.*/
|
||||
msrnum = 0x04C00001E;
|
||||
msr.hi = 0x000000000;
|
||||
msr.lo = 0x00000603C;
|
||||
wrmsr(msrnum, msr); // GX3 OK +/-
|
||||
|
||||
|
||||
/* Only do this if we are building for 5535*/
|
||||
/* */
|
||||
/* FooGlue Setup*/
|
||||
/* */
|
||||
#if 0
|
||||
/* Enable CIS mode B in FooGlue*/
|
||||
msrnum = MSR_FG + 0x10;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo &= ~3;
|
||||
msr.lo |= 2; /* ModeB*/
|
||||
msr.hi |= (0x8 << 5);
|
||||
wrmsr(msrnum, msr);
|
||||
#endif
|
||||
|
||||
/* */
|
||||
/* Disable DOT PLL. Graphics init will enable it if needed.*/
|
||||
/* */
|
||||
|
||||
// GX3: Disable DOT PLL? No. Lets tick.
|
||||
|
||||
/* msrnum = GLCP_DOTPLL;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= DOTPPL_LOWER_PD_SET;
|
||||
wrmsr(msrnum, msr); */
|
||||
|
||||
/* */
|
||||
/* Enable RSDC*/
|
||||
/* */
|
||||
msrnum = 0x1301 ;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= 0x08;
|
||||
wrmsr(msrnum, msr); //GX3 OK
|
||||
|
||||
|
||||
/* */
|
||||
/* BIST*/
|
||||
/* */
|
||||
/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
|
||||
{
|
||||
// BIST();
|
||||
}
|
||||
|
||||
|
||||
/* */
|
||||
/* Enable BTB*/
|
||||
/* */
|
||||
/* I hate to put this check here but it doesn't really work in cpubug.asm*/
|
||||
|
||||
//GX3: BTB is enabled by default
|
||||
|
||||
/* msrnum = MSR_GLCP+0x17;
|
||||
msr = rdmsr(msrnum);
|
||||
if (msr.lo >= CPU_REV_2_1){
|
||||
msrnum = CPU_PF_BTB_CONF;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
}
|
||||
|
||||
/*
|
||||
; Castle performance setting.
|
||||
; Enable Quack for fewer re-RAS on the MC
|
||||
*/
|
||||
msrnum = GLIU0_ARB;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi &= ~ARB_UPPER_DACK_EN_SET;
|
||||
msr.hi |= ARB_UPPER_QUACK_EN_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* */
|
||||
/* FPU impercise exceptions bit*/
|
||||
/* */
|
||||
/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
|
||||
msrnum = GLIU1_ARB;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi &= ~ARB_UPPER_DACK_EN_SET;
|
||||
msr.hi |= ARB_UPPER_QUACK_EN_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */
|
||||
msrnum = GLIU1_PORT_ACTIVE;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo &= ~0x880;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set the Delay Control in GLCP */
|
||||
SetDelayControl();
|
||||
|
||||
/* Enable RSDC*/
|
||||
msrnum = CPU_AC_SMM_CTL;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= SMM_INST_EN_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
|
||||
|
||||
// GX3: FPU impercise exceptions bit - what's that?
|
||||
/* {
|
||||
/* FPU imprecise exceptions bit */
|
||||
msrnum = CPU_FPU_MSR_MODE;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= FPU_IE_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
}
|
||||
|
||||
*/
|
||||
|
||||
#if 0
|
||||
/* */
|
||||
/* Cache Overides*/
|
||||
/* */
|
||||
/* This code disables the data cache. Don't execute this
|
||||
* unless you're testing something.
|
||||
*/
|
||||
/* Allow NVRam to override DM Setup*/
|
||||
/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
|
||||
{
|
||||
|
||||
msrnum = CPU_DM_CONFIG0;
|
||||
/* Power Savers (Do after BIST) */
|
||||
/* Enable Suspend on HLT & PAUSE instructions*/
|
||||
msrnum = CPU_XC_CONFIG;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
|
||||
msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
|
||||
wrmsr(msrnum, msr);
|
||||
}
|
||||
/* This code disables the instruction cache. Don't execute
|
||||
* this unless you're testing something.
|
||||
*/
|
||||
/* Allow NVRam to override IM Setup*/
|
||||
/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
|
||||
{
|
||||
msrnum = CPU_IM_CONFIG;
|
||||
|
||||
/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
|
||||
msrnum = CPU_BC_CONF_0;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= IM_CONFIG_LOWER_ICD_SET;
|
||||
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
|
||||
msr.lo &= 0x0F0FFFFFF;
|
||||
msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */
|
||||
wrmsr(msrnum, msr);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* ***************************************************************************/
|
||||
/* **/
|
||||
/* * MTestPinCheckBX*/
|
||||
/* **/
|
||||
/* * Set MTEST pins to expected values from OPTIONS.INC/NVRAM*/
|
||||
/* * This version is called when there isn't a stack available*/
|
||||
/* **/
|
||||
/* ***************************************************************************/
|
||||
static void
|
||||
MTestPinCheckBX (void){
|
||||
int msrnum;
|
||||
msr_t msr;
|
||||
|
||||
/*if (getnvram( TOKEN_MTEST_ENABLE) ==TVALUE_DISABLE ) {*/
|
||||
/* return ; */
|
||||
/* } */
|
||||
|
||||
/* Turn on MTEST*/
|
||||
msrnum = MC_CFCLK_DBUG;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET;
|
||||
/* Disable the debug clock to save power.*/
|
||||
/* NOTE: leave it enabled for fs2 debug */
|
||||
/* msrnum = GLCP_DBGCLKCTL;
|
||||
msr.hi = 0;
|
||||
msr.lo = 0;
|
||||
wrmsr(msrnum, msr);
|
||||
*/
|
||||
|
||||
msrnum = GLCP_SYS_RSTPLL /* Get SDR/DDR mode from GLCP*/;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo >>= RSTPPL_LOWER_SDRMODE_SHIFT;
|
||||
if (msr.lo & 1) {
|
||||
msrnum = MC_CFCLK_DBUG; /* Turn on SDR MTEST stuff*/
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= CFCLK_LOWER_SDCLK_SET;
|
||||
msr.hi |= CFCLK_UPPER_MTST_DQS_EN_SET;
|
||||
/* Setup throttling delays to proper mode if it is ever enabled. */
|
||||
msrnum = GLCP_TH_OD;
|
||||
msr.hi = 0;
|
||||
msr.lo = 0x00000603C;
|
||||
wrmsr(msrnum, msr);
|
||||
}
|
||||
|
||||
/* Lock the cache down here.*/
|
||||
__asm__("wbinvd\n");
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -46,7 +46,6 @@ static void model_lx_init(device_t dev)
|
|||
printk_debug("model_lx_init\n");
|
||||
|
||||
/* Turn on caching if we haven't already */
|
||||
|
||||
x86_enable_cache();
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
|
|
@ -60,7 +59,7 @@ static void model_lx_init(device_t dev)
|
|||
outb(0x02,0x92);
|
||||
printk_debug("A20 (0x92): %d\n",inb(0x92));
|
||||
|
||||
printk_debug("model_lx_init DONE\n");
|
||||
printk_debug("CPU model_lx_init DONE\n");
|
||||
};
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
|
|
|
|||
|
|
@ -20,8 +20,6 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* ***************************************************************************/
|
||||
|
||||
/* ***************************************************************************/
|
||||
/* **/
|
||||
/* * StartTimer1*/
|
||||
|
|
@ -41,6 +39,8 @@ void
|
|||
SystemPreInit(void){
|
||||
|
||||
/* they want a jump ... */
|
||||
__asm__("jmp .+2\ninvd\njmp.+2\n");
|
||||
#ifndef USE_DCACHE_RAM
|
||||
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
|
||||
#endif
|
||||
StartTimer1();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -69,6 +69,9 @@
|
|||
* software, even if advised of the possibility of such damage.
|
||||
*
|
||||
* $Id: vsmsetup.c,v 1.8 2006/09/08 12:47:57 andrei Exp $
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices
|
||||
*
|
||||
*--------------------------------------------------------------------*/
|
||||
|
||||
/* Modified to be a self sufficient plug in so that it can be used
|
||||
|
|
@ -300,13 +303,13 @@ void do_vsmbios(void)
|
|||
printk_err("do_vsmbios\n");
|
||||
/* clear vsm bios data area */
|
||||
for (i = 0x400; i < 0x500; i++) {
|
||||
*(unsigned char *) i = 0;
|
||||
*(volatile unsigned char *) i = 0;
|
||||
}
|
||||
|
||||
/* declare rom address here - keep any config data out of the way
|
||||
* of core LXB stuff */
|
||||
|
||||
/* this is the base of rom on the GX2 at present. At some point, this has to be
|
||||
/* this is the base of rom on the LX at present. At some point, this has to be
|
||||
* much better parameterized
|
||||
*/
|
||||
//rom = 0xfff80000;
|
||||
|
|
@ -314,8 +317,10 @@ void do_vsmbios(void)
|
|||
/* the VSA starts at the base of rom - 64 */
|
||||
//rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024);
|
||||
|
||||
rom = 0xfffc8000;
|
||||
//rom = 0xfffc8000;
|
||||
|
||||
//VSA is cat onto the end after LB builds
|
||||
rom = ((unsigned long) 0) - (ROM_SIZE + 36 * 1024);
|
||||
buf = (unsigned char *) VSA2_BUFFER;
|
||||
olen = unrv2b((uint8_t *)rom, buf, &ilen);
|
||||
printk_debug("buf ilen %d olen%d\n", ilen, olen);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
/* standard AMD post definitions -- might as well use them. */
|
||||
#define POST_Output_Port (0x080) /* port to write post codes to*/
|
||||
|
||||
#define POST_preSioInit (0x000) /* geode.asm*/
|
||||
#define POST_clockInit (0x001) /* geode.asm*/
|
||||
#define POST_CPURegInit (0x002) /* geode.asm*/
|
||||
#define POST_UNREAL (0x003) /* geode.asm*/
|
||||
#define POST_CPUMemRegInit (0x004) /* geode.asm*/
|
||||
#define POST_CPUTest (0x005) /* geode.asm*/
|
||||
#define POST_memSetup (0x006) /* geode.asm*/
|
||||
#define POST_memSetUpStack (0x007) /* geode.asm*/
|
||||
#define POST_memTest (0x008) /* geode.asm*/
|
||||
#define POST_shadowRom (0x009) /* geode.asm*/
|
||||
#define POST_memRAMoptimize (0x00A) /* geode.asm*/
|
||||
#define POST_cacheInit (0x00B) /* geode.asm*/
|
||||
#define POST_northBridgeInit (0x00C) /* geode.asm*/
|
||||
#define POST_chipsetInit (0x00D) /* geode.asm*/
|
||||
#define POST_sioTest (0x00E) /* geode.asm*/
|
||||
#define POST_pcATjunk (0x00F) /* geode.asm*/
|
||||
|
||||
|
||||
#define POST_intTable (0x010) /* geode.asm*/
|
||||
#define POST_memInfo (0x011) /* geode.asm*/
|
||||
#define POST_romCopy (0x012) /* geode.asm*/
|
||||
#define POST_PLLCheck (0x013) /* geode.asm*/
|
||||
#define POST_keyboardInit (0x014) /* geode.asm*/
|
||||
#define POST_cpuCacheOff (0x015) /* geode.asm*/
|
||||
#define POST_BDAInit (0x016) /* geode.asm*/
|
||||
#define POST_pciScan (0x017) /* geode.asm*/
|
||||
#define POST_optionRomInit (0x018) /* geode.asm*/
|
||||
#define POST_ResetLimits (0x019) /* geode.asm*/
|
||||
#define POST_summary_screen (0x01A) /* geode.asm*/
|
||||
#define POST_Boot (0x01B) /* geode.asm*/
|
||||
#define POST_SystemPreInit (0x01C) /* geode.asm*/
|
||||
#define POST_ClearRebootFlag (0x01D) /* geode.asm*/
|
||||
#define POST_GLIUInit (0x01E) /* geode.asm*/
|
||||
#define POST_BootFailed (0x01F) /* geode.asm*/
|
||||
|
||||
|
||||
#define POST_CPU_ID (0x020) /* cpucpuid.asm*/
|
||||
#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/
|
||||
#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/
|
||||
#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/
|
||||
#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/
|
||||
#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/
|
||||
#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/
|
||||
#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/
|
||||
#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/
|
||||
#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/
|
||||
#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/
|
||||
#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/
|
||||
#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/
|
||||
#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/
|
||||
#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/
|
||||
#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/
|
||||
|
||||
|
||||
|
||||
/* PCI config*/
|
||||
#define P80_PCICFG (0x030) /* pcispace.asm*/
|
||||
|
||||
|
||||
/* PCI io*/
|
||||
#define P80_PCIIO (0x040) /* pcispace.asm*/
|
||||
|
||||
|
||||
/* PCI memory*/
|
||||
#define P80_PCIMEM (0x050) /* pcispace.asm*/
|
||||
|
||||
|
||||
/* SIO*/
|
||||
#define P80_SIO (0x060) /* *sio.asm*/
|
||||
|
||||
/* Memory Setp*/
|
||||
#define P80_MEM_SETUP (0x070) /* docboot meminit*/
|
||||
#define POST_MEM_SETUP (0x070) /* memsize.asm*/
|
||||
#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/
|
||||
#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/
|
||||
#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/
|
||||
#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/
|
||||
#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/
|
||||
#define POST_MEM_ENABLE (0x076) /* memsize.asm*/
|
||||
#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/
|
||||
#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/
|
||||
#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/
|
||||
#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/
|
||||
#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/
|
||||
#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/
|
||||
#define ERROR_BANK_SET (0x07d) /* memsize.asm*/
|
||||
#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/
|
||||
#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/
|
||||
|
||||
|
||||
#define POST_UserPreInit (0x080) /* geode.asm*/
|
||||
#define POST_UserPostInit (0x081) /* geode.asm*/
|
||||
#define POST_Equipment_check (0x082) /* geode.asm*/
|
||||
#define POST_InitNVRAMBX (0x083) /* geode.asm*/
|
||||
#define POST_NoPIRTable (0x084) /* pci.asm*/
|
||||
#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/
|
||||
#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/
|
||||
#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/
|
||||
#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/
|
||||
#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/
|
||||
#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/
|
||||
#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/
|
||||
#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/
|
||||
#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/
|
||||
#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/
|
||||
|
||||
|
||||
#define POST_STACK_SETUP (0x090) /* memstack.asm*/
|
||||
#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/
|
||||
#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/
|
||||
#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/
|
||||
#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/
|
||||
#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/
|
||||
#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/
|
||||
#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/
|
||||
#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/
|
||||
|
||||
|
||||
#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/
|
||||
#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/
|
||||
#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/
|
||||
#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/
|
||||
#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/
|
||||
#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/
|
||||
#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/
|
||||
|
||||
|
||||
#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/
|
||||
#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/
|
||||
#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/
|
||||
#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/
|
||||
#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/
|
||||
#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/
|
||||
#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/
|
||||
|
||||
|
||||
#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/
|
||||
#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/
|
||||
#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/
|
||||
#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/
|
||||
#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/
|
||||
#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/
|
||||
#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/
|
||||
#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/
|
||||
#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/
|
||||
#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/
|
||||
#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/
|
||||
#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/
|
||||
#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/
|
||||
#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/
|
||||
|
||||
#define POST_RCONFInitError (0x0CE) /* cache.asm*/
|
||||
#define POST_CacheInitError (0x0CF) /* cache.asm*/
|
||||
|
||||
|
||||
#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/
|
||||
#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/
|
||||
#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/
|
||||
#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/
|
||||
#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/
|
||||
#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/
|
||||
#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/
|
||||
#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/
|
||||
#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/
|
||||
#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/
|
||||
#define POST_ROM_POSTUNCOMPRESS (0x0DE)
|
||||
|
||||
|
||||
#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/
|
||||
#define POST_PreChipsetInit (0x0E1) /* geode.asm*/
|
||||
#define POST_LateChipsetInit (0x0E2) /* geode.asm*/
|
||||
#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/
|
||||
|
||||
|
||||
#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,22 +1,11 @@
|
|||
/* <LIC_AMD_STD>
|
||||
* Copyright (C) 2003-2005 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* </LIC_AMD_STD> */
|
||||
//<CTL_AMD_STD>
|
||||
//$Id: //bios/main/vsa_ii/inc/vr.h#18 $
|
||||
//$Header: //bios/main/vsa_ii/inc/vr.h#18 $
|
||||
//$Date: 2005/09/29 $
|
||||
//$DateTime: 2005/09/29 11:07:14 $
|
||||
//$Change: 65425 $
|
||||
//$File: //bios/main/vsa_ii/inc/vr.h $
|
||||
//$Revision: #18 $
|
||||
//$Author: johnk $
|
||||
//</CTL_AMD_STD>
|
||||
//<DOC_AMD_STD>
|
||||
// Virtual Register USAGE:
|
||||
//
|
||||
// Index: AH = Class, AL = Parameter_ID
|
||||
// Data: AX = data
|
||||
//</DOC_AMD_STD>
|
||||
/*
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef CPU_AMD_VR_H
|
||||
#define CPU_AMD_VR_H
|
||||
|
||||
#define VRC_INDEX 0xAC1C // Index register
|
||||
#define VRC_DATA 0xAC1E // Data register
|
||||
|
|
@ -484,3 +473,28 @@
|
|||
#define MAX_THERMAL VRC_THERMAL_SMB_DATA
|
||||
|
||||
#define MAX_VR_CLASS VRC_THERMAL
|
||||
|
||||
/*
|
||||
* Write to a Virtual Register
|
||||
* AX = Class/Index
|
||||
* CX = data to write
|
||||
*/
|
||||
static inline void vrWrite(uint16_t wClassIndex, uint16_t wData)
|
||||
{
|
||||
outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
|
||||
outw(wData, VRC_DATA);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read from a Virtual Register
|
||||
* AX = Class/Index
|
||||
* Returns a 16-bit word of data
|
||||
*/
|
||||
static inline uint16_t vrRead(uint16_t wClassIndex)
|
||||
{
|
||||
uint16_t wData;
|
||||
outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
|
||||
wData = inw(VRC_DATA);
|
||||
return wData;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -85,6 +85,17 @@
|
|||
#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */
|
||||
#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */
|
||||
|
||||
/* DRAM specifications use the following naming conventions for SPD locations */
|
||||
#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME
|
||||
#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE
|
||||
#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY
|
||||
#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
|
||||
#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE
|
||||
#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME
|
||||
#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
|
||||
#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
|
||||
|
||||
|
||||
/* SPD_MEMORY_TYPE values. */
|
||||
#define SPD_MEMORY_TYPE_FPM_DRAM 1
|
||||
#define SPD_MEMORY_TYPE_EDO 2
|
||||
|
|
|
|||
Loading…
Reference in New Issue