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mb/google/brya/var/kinox: Change HDMI port form DDPC to DDP2 

Modify GPIOs according to SOC_GPIO_Table_0629.xlsx.

- GPP_A21 from TCP_DP1_CTRLCLK to NC
- GPP_A22 from TCP_DP1_CTRLDATA to NC
- GPP_E20 from NC to TCP_DP1_CTRLCLK (Native Function 1)
- GPP_E21 from NC to TCP_DP1_CTRLDATA (Native Function 1)

BUG=b:237468533
TEST=emerge-brask coreboot

Change-Id: I8e7d343731efbfc04304d52a3493ab30b8a739b0
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit is contained in:
ericky_cheng 2022-06-30 17:08:56 +08:00 committed by Felix Held
parent 42dae32e6c
commit bc8ab7bf6e
1 changed files with 9 additions and 8 deletions
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17
src/mainboard/google/brya/variants/kinox/gpio.c
View File

@ -16,10 +16,10 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_A19, NONE), PAD_NC(GPP_A19, NONE),
/* A20 : DDSP_HPD2 ==> TCP_DP1_HPD */ /* A20 : DDSP_HPD2 ==> TCP_DP1_HPD */
PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
/* A21 : DDPC_CTRCLK ==> TCP_DP1_CTRLCLK */ /* A21 : DDPC_CTRCLK ==> NC */
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), PAD_NC(GPP_A21, NONE),
/* A22 : DDPC_CTRLDATA ==> TCP_DP1_CTRLDATA */ /* A22 : DDPC_CTRLDATA ==> NC */
PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), PAD_NC(GPP_A22, NONE),
/* B2 : VRALERT# ==> TP153 */ /* B2 : VRALERT# ==> TP153 */
PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B2, NONE),
@ -54,10 +54,11 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E18, NONE), PAD_NC(GPP_E18, NONE),
/* E19 : DDP1_CTRLDATA ==> NC */ /* E19 : DDP1_CTRLDATA ==> NC */
PAD_NC(GPP_E19, NONE), PAD_NC(GPP_E19, NONE),
/* E20 : DDP2_CTRLCLK ==> NC */ /* E20 : DDP2_CTRLCLK ==> TCP_DP1_CTRLCLK */
PAD_NC(GPP_E20, NONE), PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* E21 : DDP2_CTRLDATA ==> NC */ /* E21 : DDP2_CTRLDATA ==> TCP_DP1_CTRLDATA */
PAD_NC(GPP_E21, NONE), PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* F11 : THC1_SPI2_CLK ==> NC */ /* F11 : THC1_SPI2_CLK ==> NC */
PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),