intel/strago: Fix some CHROMEOS guards
MAINBOARD_HAS_CHROMEOS always evaluates true for this board. The commentary about get_write_protect_state() was wrong, it's currently only called in ramstage. Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -2,11 +2,11 @@
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bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
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romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c
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ramstage-y += ec.c
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ramstage-y += gpio.c
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ramstage-y += irqroute.c
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ramstage-y += ramstage.c
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ramstage-y += w25q64.c
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@ -23,14 +23,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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int get_write_protect_state(void)
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{
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/*
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* The vboot loader queries this function in romstage. The GPIOs have
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* This function might get queried early in romstage. The GPIOs have
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* not been set up yet as that configuration is done in ramstage.
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* Configuring this GPIO as input so that there isn't any ambiguity
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* in the reading.
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*/
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#if ENV_ROMSTAGE
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gpio_input_pullup(WP_GPIO);
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#endif
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if (ENV_ROMSTAGE_OR_BEFORE)
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gpio_input_pullup(WP_GPIO);
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/* WP is enabled when the pin is reading high. */
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return !!gpio_get(WP_GPIO);
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