GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration 

This patch performs additional SPI lock configuration as per Intel
Flash Security Specification.

BUG=b:211954778
TEST=Able to build google/brya and verified all flash security
recommendations are being met.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-04-13 21:59:43 +05:30 committed by Felix Held
parent 5685cbb958
commit bca2f02ab7
1 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/soc/intel/common/pch/lockdown/lockdown.c
View File

@ -57,9 +57,18 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown)
/* Discrete Lock Flash PR registers */
fast_spi_pr_dlock();
/* Check if SPI transaction is pending */
fast_spi_cycle_in_progress();
/* Clear any outstanding status bits like AEL, FCERR, FDONE, SAF etc. */
fast_spi_clear_outstanding_status();
/* Lock FAST_SPIBAR */
fast_spi_lock_bar();
/* Set Vendor Component Lock (VCL) */
fast_spi_vscc0_lock();
/* Set BIOS Interface Lock, BIOS Lock */
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
/* BIOS Interface Lock */