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panther: update chromeos.c 

The google mainboards were updated to unconditionally include
chromeos.c except for panther.

Change-Id: I35bbd56326ee0f94ee542bae28f9c23980e9a9ed
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6874
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Isaac Christensen 2014-09-11 11:02:29 -06:00
parent 3f0f300bcf
commit bca446d471
2 changed files with 8 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/panther/Makefile.inc
View File

@ -17,8 +17,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += chromeos.c
ramstage-y += lan.c ramstage-y += lan.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

25
src/mainboard/google/panther/chromeos.c
View File

@ -19,7 +19,7 @@
#include <string.h> #include <string.h>
#include <arch/io.h> #include <arch/io.h>
#include <boot/coreboot_tables.h> #include <bootmode.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
@ -32,23 +32,10 @@
#define FLAG_REC_MODE 1 #define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2 #define FLAG_DEV_MODE 2
#define GPIO_COUNT 6
#define ACTIVE_LOW 0
#define ACTIVE_HIGH 1
#ifndef __PRE_RAM__ #ifndef __PRE_RAM__
static void fill_lb_gpio(struct lb_gpio *gpio, int num, #include <boot/coreboot_tables.h>
int polarity, const char *name, int force)
{ #define GPIO_COUNT 6
memset(gpio, 0, sizeof(*gpio));
gpio->port = num;
gpio->polarity = polarity;
if (force >= 0)
gpio->value = force;
else if (num >= 0)
gpio->value = get_gpio(num);
strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
}
void fill_lb_gpios(struct lb_gpios *gpios) void fill_lb_gpios(struct lb_gpios *gpios)
{ {
@ -65,7 +52,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
get_developer_mode_switch()); get_developer_mode_switch());
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1);
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
} }
#endif #endif
@ -97,7 +84,7 @@ int get_recovery_mode_switch(void)
} }
#ifdef __PRE_RAM__ #ifdef __PRE_RAM__
void save_chromeos_gpios(void) void init_bootmode_straps(void)
{ {
u32 flags = 0; u32 flags = 0;