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mb/google/brya: Enable ACPI and add ACPI table 

Enable ACPI configuration and add DSDT ACPI table.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Eric Lai 2020-11-26 14:20:48 +08:00 committed by Tim Wawrzynczak
parent e1d7d8464c
commit bca5bdb056
2 changed files with 20 additions and 0 deletions
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1
src/mainboard/google/brya/Kconfig
View File

@ -1,6 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_BRYA config BOARD_GOOGLE_BASEBOARD_BRYA
def_bool n def_bool n
select BOARD_ROMSIZE_KB_32768 select BOARD_ROMSIZE_KB_32768
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select SOC_INTEL_ALDERLAKE select SOC_INTEL_ALDERLAKE

19
src/mainboard/google/brya/dsdt.asl
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@ -11,4 +11,23 @@ DefinitionBlock(
0x20110725 // OEM revision 0x20110725 // OEM revision
) )
{ {
/* Some generic macros */
#include <soc/intel/common/acpi/platform.asl>
/* global NVS and variables */
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
}
}
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl>
} }