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X201: Move early nehalem S3 magic to right place. 

This MCH magic needs to be done before GPIO.

Now S3 (Suspend-to-RAM) works on X201.

Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4632
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Vladimir Serbinenko 2014-01-09 11:13:18 +01:00
parent f7a42de725
commit bca985557e
3 changed files with 9 additions and 16 deletions
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12
src/mainboard/lenovo/x201/romstage.c
View File

@ -240,25 +240,19 @@ void main(unsigned long bist)
if (bist == 0) if (bist == 0)
enable_lapic(); enable_lapic();
/* Force PCIRST# */ nehalem_early_initialization(NEHALEM_MOBILE);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, SBR); pch_enable_lpc();
udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, 0);
/* Enable USB Power. We need to do it early for usbdebug to work. */ /* Enable USB Power. We need to do it early for usbdebug to work. */
ec_set_bit(0x3b, 4); ec_set_bit(0x3b, 4);
pch_enable_lpc();
/* Enable GPIOs */ /* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&x201_gpio_map); setup_pch_gpios(&x201_gpio_map);
nehalem_early_initialization(NEHALEM_MOBILE);
/* This should probably go away. Until now it is required /* This should probably go away. Until now it is required
* and mainboard specific * and mainboard specific

6
src/northbridge/intel/nehalem/early_init.c
View File

@ -166,4 +166,10 @@ void nehalem_early_initialization(int chipset_type)
pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR); pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Magic for S3 resume. Must be done early. */
if (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) {
MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;
}
} }

7
src/northbridge/intel/nehalem/raminit.c
View File

@ -3815,13 +3815,6 @@ void raminit(const int s3resume)
unsigned channel, slot, lane, rank; unsigned channel, slot, lane, rank;
int i; int i;
struct raminfo info; struct raminfo info;
if (s3resume) {
read_mchbar32(0x1e8);
write_mchbar32(0x1e8, 0x6);
read_mchbar32(0x1e8);
write_mchbar32(0x1e8, 0x4);
}
u8 x2ca8; u8 x2ca8;
gav(x2ca8 = read_mchbar8(0x2ca8)); gav(x2ca8 = read_mchbar8(0x2ca8));