diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 64258b24ca..62272c0927 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -137,6 +137,15 @@ struct soc_amd_picasso_config {
 
 	uint8_t has_usb2_phy_tune_params;
 	struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT];
+	enum {
+		USB_OC_PIN_0	= 0x0,
+		USB_OC_PIN_1	= 0x1,
+		USB_OC_PIN_2	= 0x2,
+		USB_OC_PIN_3	= 0x3,
+		USB_OC_PIN_4	= 0x4,
+		USB_OC_PIN_5	= 0x5,
+		USB_OC_NONE	= 0xf,
+	} usb_port_overcurrent_pin[USB_PORT_COUNT];
 };
 
 typedef struct soc_amd_picasso_config config_t;
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 8e6703e436..1dbb8e57b5 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -98,17 +98,28 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg)
 static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
 			const struct soc_amd_picasso_config *cfg)
 {
+	size_t i;
+
 	ASSERT(FSPS_UPD_USB2_PORT_COUNT == USB_PORT_COUNT);
+	/* each OC mapping in xhci_oc_pin_select is 4 bit per USB port */
+	ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT);
 
 	scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
 
 	if (cfg->has_usb2_phy_tune_params) {
-		for (size_t i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {
+		for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {
 			memcpy(scfg->fch_usb_2_port_phy_tune[i],
 				&cfg->usb_2_port_tune_params[i],
 				sizeof(scfg->fch_usb_2_port_phy_tune[0]));
 		}
 	}
+
+	/* lowest nibble of xhci_oc_pin_select corresponds to OC mapping of first USB port */
+	for (i = 0; i < USB_PORT_COUNT; i++) {
+		scfg->xhci_oc_pin_select &= ~(0xf << (i * 4));
+		scfg->xhci_oc_pin_select |=
+			(cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4);
+	}
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)