try to unify timing initialization across those boards that need it...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/asus/a8n_e/romstage.c

@@ -63,11 +63,6 @@
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
-static void memreset_setup(void)
-{
-	/* Nothing to do. */
-}
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 	/* Nothing to do. */
@@ -181,7 +176,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	dump_smbus_registers();
 #endif
 
-	memreset_setup();
 	sdram_initialize(nodes, ctrl);
 
 #if 0

src/mainboard/gigabyte/m57sli/romstage.c

@@ -265,6 +265,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         }
 #endif
 
+	init_timer(); // Need to use TMICT to synconize FID/VID
+
         needs_reset |= optimize_link_coherent_ht();
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
         needs_reset |= mcp55_early_setup_x();
@@ -281,9 +283,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         enable_smbus(); 
 
-        //do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
-//        init_timer(); // Need to use TMICT to synconize FID/VID
 
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/msi/ms7260/romstage.c

@@ -237,6 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 #endif
 
+	init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
 	needs_reset |= optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	needs_reset |= mcp55_early_setup_x();
@@ -253,9 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	enable_smbus();
 
-	/* Do we need apci timer, tsc...., only debug need it for better output */
 	/* All AP stopped? */
-	// init_timer(); /* Need to use TMICT to synconize FID/VID. */
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/msi/ms9282/romstage.c

@@ -199,10 +199,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
+	init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
 	needs_reset = optimize_link_coherent_ht();
-
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
 	needs_reset |= mcp55_early_setup_x();
 
         if (needs_reset) {
@@ -226,6 +226,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
        post_cache_as_ram();
-
 }
 

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -58,6 +58,8 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
@@ -262,6 +264,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	msr=rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
+	init_timer(); /* Need to use TMICT to synconize FID/VID. */
 
 	wants_reset = mcp55_early_setup_x();
 

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -250,6 +250,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	}
 #endif
+	init_timer(); /* Need to use TMICT to synconize FID/VID. */
 
 	needs_reset |= optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
@@ -267,9 +268,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	enable_smbus();
 
-	//do we need apci timer, tsc...., only debug need it for better output
 	/* all ap stopped? */
-//	init_timer(); // Need to use TMICT to synconize FID/VID
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/supermicro/h8dme/romstage.c

@@ -46,16 +46,14 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-
 #include "pc80/serial.c"
 #include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 
-// #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+// for enable the FAN
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -313,7 +311,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 #endif
 
-#if 1
+	init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
 	needs_reset |= optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	needs_reset |= mcp55_early_setup_x();
@@ -323,7 +322,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		print_info("ht reset -\n");
 		soft_reset();
 	}
-#endif
+
 	allow_all_aps_stop(bsp_apicid);
 
 	//It's the time to set ctrl in sysinfo now;
@@ -331,9 +330,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	enable_smbus();		/* enable in sio_setup */
 
-	//do we need apci timer, tsc...., only debug need it for better output
 	/* all ap stopped? */
-//        init_timer(); // Need to use TMICT to synconize FID/VID
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/supermicro/h8dmr/romstage.c

@@ -49,16 +49,14 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-
 #include "pc80/serial.c"
 #include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 
-//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+// for enable the FAN
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -213,12 +211,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
 #if SET_FIDVID == 1
-
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
-
         }
 
         enable_fid_change();
@@ -231,12 +227,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "end   msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
-
         }
 #endif
 
-#if 1
+	init_timer(); // Need to use TMICT to synconize FID/VID
+
         needs_reset |= optimize_link_coherent_ht();
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
         needs_reset |= mcp55_early_setup_x();
@@ -246,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                 print_info("ht reset -\n");
               	soft_reset();
         }
-#endif
+
         allow_all_aps_stop(bsp_apicid);
 
         //It's the time to set ctrl in sysinfo now;
@@ -254,9 +250,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //        enable_smbus(); /* enable in sio_setup */
 
-        //do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
-//        init_timer(); // Need to use TMICT to synconize FID/VID
 
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -44,18 +44,18 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "pc80/serial.c"
 #include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_10xxx_rev.h>
 
-//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+// for enable the FAN
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
+#include "cpu/amd/model_10xxx/apic_timer.c"
+#include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@ -103,8 +103,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/microcode/microcode.c"
@@ -120,21 +118,23 @@ static void sio_setup(void)
 {
 	uint32_t dword;
 	uint8_t byte;
+
 	enable_smbus();
-//	smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
+	// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
-	smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
+	/* set FAN ctrl to DC mode */
+	smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff);
 
-        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
 	byte |= 0x20;
-        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
 
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
-        dword |= (1<<0);
+	dword |= (1 << 0);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
 
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
-        dword |= (1<<16);
+	dword |= (1 << 16);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
 
 }
 
@@ -142,7 +142,8 @@ static void sio_setup(void)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-  struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
+		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 	u32 bsp_apicid = 0;
 	u32 val;
@@ -184,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo + 1);
 	printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
@@ -208,6 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x36);
 
 	/* wait for all the APs core0 started by finalize_node_setup. */
+
 	/* FIXME: A bunch of cores are going to start output to serial at once.
 	 * It would be nice to fixup prink spinlocks for ROM XIP mode.
 	 * I think it could be done by putting the spinlock flag in the cache
@@ -227,7 +229,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 #if SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
+		msr.hi, msr.lo);
 
 	/* FIXME: The sb fid change may survive the warm reset and only
 	 * need to be done once.*/
@@ -244,10 +247,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
- msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n",
+	       msr.hi, msr.lo);
 #endif
 
+	init_timer(); // Need to use TMICT to synconize FID/VID
+
 	wants_reset = mcp55_early_setup_x();
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
@@ -258,28 +264,26 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	if (wants_reset)
-   printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
+		printk(BIOS_DEBUG, "mcp55_early_setup_x wants additional reset!\n");
 
 	post_code(0x3B);
 
-/* It's the time to set ctrl in sysinfo now; */
+	/* It's the time to set ctrl in sysinfo now; */
-printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
-fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
-post_code(0x3D);
+	post_code(0x3D);
 
-//printk(BIOS_DEBUG, "enable_smbus()\n");
+	// printk(BIOS_DEBUG, "enable_smbus()\n");
-//        enable_smbus(); /* enable in sio_setup */
+	// enable_smbus(); /* enable in sio_setup */
 
-post_code(0x40);
+	post_code(0x40);
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
 	post_code(0x41);
 
-// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+	// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
- post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
+	post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
 	post_code(0x42);     // Should never see this post code.
-
 }
-

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -44,19 +44,18 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-
 #include "pc80/serial.c"
 #include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_10xxx_rev.h>
 
-//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+// for enable the FAN
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
+#include "cpu/amd/model_10xxx/apic_timer.c"
+#include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@ -293,6 +292,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 #endif
 
+	init_timer(); // Need to use TMICT to synconize FID/VID
+
  wants_reset = mcp55_early_setup_x();
 
  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */

src/mainboard/supermicro/x6dai_g/romstage.c

@@ -10,6 +10,8 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 #include "lib/ramtest.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
 #include "northbridge/intel/e7525/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"

src/mainboard/supermicro/x6dhe_g/romstage.c

@@ -10,6 +10,8 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 #include "lib/ramtest.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"

src/mainboard/tyan/s2912/romstage.c

@@ -245,6 +245,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 #endif
 
+	init_timer(); // Need to use TMICT to synconize FID/VID
+
 	needs_reset |= optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	needs_reset |= mcp55_early_setup_x();
@@ -262,9 +264,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	enable_smbus();
 
-	//do we need apci timer, tsc...., only debug need it for better output
 	/* all ap stopped? */
-//	init_timer(); // Need to use TMICT to synconize FID/VID
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -59,6 +59,8 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 
+#include "cpu/amd/model_10xxx/apic_timer.c"
+#include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@ -254,6 +256,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
+	init_timer(); // Need to use TMICT to synconize FID/VID
+
 	wants_reset = mcp55_early_setup_x();
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */

src/southbridge/intel/esb6300/esb6300_smbus.c

@@ -8,10 +8,15 @@
 #include "esb6300.h"
 #include "esb6300_smbus.h"
 
-static int lsmbus_read_byte(device_t dev, uint8_t address)
+static int lsmbus_read_byte(device_t dev, u8 address)
 {
+	u16 device;
 	struct resource *res;
-	res = find_resource(dev, 0x20);
+	struct bus *pbus;
+
+	device = dev->path.i2c.device;
+	pbus = get_pbus_smbus(dev);
+	res = find_resource(pbus->dev, 0x20);
 
 	return do_smbus_read_byte(res->base, device, address);
 }

src/southbridge/intel/esb6300/esb6300_smbus.h

@@ -40,8 +40,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 	return loops?0:-1;
 }
 
-#ifdef UNUSED_CODE
+static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
-static int smbus_wait_until_blk_done(unsigned smbus_io_base)
 {
 	unsigned loops = SMBUS_TIMEOUT;
 	unsigned char byte;
@@ -53,7 +52,6 @@ static int smbus_wait_until_blk_done(unsigned smbus_io_base)
 	} while((byte&(1<<7)) == 0);
 	return loops?0:-1;
 }
-#endif
 
 static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
 {

src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c

@@ -134,9 +134,6 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned
 
 }
 
-#include "src/pc80/udelay_io.c"
-#include "src/lib/delay.c"
-
 static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
 {
 	uint32_t tgio_ctrl;