src/mainboard/emulation/qemu-power9: add RAM detection
Change-Id: Ie333294c7a311f6d47bdfbd1fc3cec0128cf63e7 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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@ -1,11 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cbmem.h>
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#include <cbmem.h>
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#include <ramdetect.h>
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void *cbmem_top_chipset(void)
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void *cbmem_top_chipset(void)
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{
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{
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/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
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return (void *)(probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB);
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/* For now, last 1M of 4G */
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void *ptr = (void *) (4ULL * GiB - 1 * MiB);
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return ptr;
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}
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}
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@ -8,6 +8,7 @@ static void mainboard_enable(struct device *dev)
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{
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{
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if (!dev)
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if (!dev)
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die("No dev0; die\n");
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die("No dev0; die\n");
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ram_resource(dev, 0, 0, (unsigned long)cbmem_top() / KiB);
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}
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}
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struct chip_operations mainboard_ops = {
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struct chip_operations mainboard_ops = {
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@ -10,14 +10,14 @@ SECTIONS
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BOOTBLOCK(0, 32K)
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BOOTBLOCK(0, 32K)
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STACK(0x8000, 32K)
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ROMSTAGE(0xf00000, 1M)
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STACK(0x1000000, 32K)
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RAMSTAGE(0x1008000, 1M)
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PRERAM_CBMEM_CONSOLE(0x10000, 128K)
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FMAP_CACHE(0x1108000, 4K)
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FMAP_CACHE(0x30000, 4K)
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CBFS_MCACHE(0x1109000, 8K)
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CBFS_MCACHE(0x31000, 8K)
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TIMESTAMP(0x110b000, 4K)
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TIMESTAMP(0x33000, 4K)
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CBFS_CACHE(0x110c000, 512K)
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CBFS_CACHE(0x34000, 512K)
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PRERAM_CBMEM_CONSOLE(0x118c000, 128K)
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ROMSTAGE(0x100000, 1M)
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RAMSTAGE(0x300000, 5M)
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}
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}
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@ -1,10 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cbmem.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <program_loading.h>
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#include <program_loading.h>
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void main(void)
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void main(void)
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{
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{
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console_init();
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console_init();
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cbmem_initialize_empty();
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run_ramstage();
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run_ramstage();
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}
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}
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