mb/google/brya/var/agah: Update NVVDD VR PGOOD GPIO

For board revs 3 and later, the PG pin for the NVVDD VR moved from
GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that
this code will write the correct GPIO # to depending on the board rev,
and we'll use that instead.

BUG=b:239721380
TEST=still works on board rev 2

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>

src/mainboard/google/brya/acpi/power.asl

@@ -7,7 +7,6 @@
 #define GPIO_NV33_PWR_EN	GPP_A21
 #define GPIO_NV33_PG		GPP_A22
 #define GPIO_NVVDD_PWR_EN	GPP_E0
-#define GPIO_NVVDD_PG		GPP_E16
 #define GPIO_PEXVDD_PWR_EN	GPP_E10
 #define GPIO_PEXVDD_PG		GPP_E17
 #define GPIO_FBVDD_PWR_EN	GPP_A19
@@ -22,6 +21,15 @@
 /* 250ms in "Timer" units (i.e. 100ns increments) */
 #define MIN_OFF_TIME_TIMERS	2500000
 
+/*
+ * For board revs 3 and later, the PG pin for the NVVDD VR moved from
+ * GPP_E16 to GPP_E3. To accommodate this, this DSDT contains a Name
+ * that the `variant.c` code will write the correct GPIO # to depending
+ * on the board rev, and we'll use that instead.
+ */
+/* Dynamically-assigned NVVDD PG GPIO, set in _INI in SSDT */
+Name (NVPG, 0)
+
 /* Optimus Power Control State */
 Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE)
 
@@ -72,7 +80,7 @@ Method (GC6I, 0, Serialized)
 
 	/* Deassert EN_PPVAR_GPU_NVVDD */
 	\_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN)
-	GPPL (GPIO_NVVDD_PG, 0, 20)
+	GPPL (NVPG, 0, 20)
 	Sleep (2)
 
 	/* Assert GPU_PERST_L */
@@ -95,7 +103,7 @@ Method (GC6O, 0, Serialized)
 
 	/* Ramp up NVVDD */
 	\_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN)
-	GPPL (GPIO_NVVDD_PG, 1, 4)
+	GPPL (NVPG, 1, 4)
 
 	/* Ramp up PEXVDD */
 	 \_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN)
@@ -141,7 +149,7 @@ Method (PGON, 0, Serialized)
 
 	/* Ramp up NVVDD rail */
 	\_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN)
-	GPPL (GPIO_NVVDD_PG, 1, 5)
+	GPPL (NVPG, 1, 5)
 
 	/* Ramp up PEXVDD rail */
 	\_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN)
@@ -190,7 +198,7 @@ Method (PGOF, 0, Serialized)
 
 	/* Ramp down NVVDD and let rail discharge to <10% */
 	\_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN)
-	GPPL (GPIO_NVVDD_PG, 0, 20)
+	GPPL (NVPG, 0, 20)
 	Sleep (2)
 
 	/* Ramp down NV33 and let rail discharge to <10% */

src/mainboard/google/brya/variants/agah/gpio.c

@@ -77,8 +77,8 @@ static const struct pad_config override_gpio_table[] = {
 
 	/* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X */
 	PAD_CFG_GPO(GPP_E0, 0, DEEP),
-	/* E3  : PROC_GP0 ==> NC */
+	/* E3  : PROC_GP0 ==> PG_PPVAR_GPU_NVVDD_X_OD (board rev 3 and later) */
-	PAD_NC(GPP_E3, NONE),
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
 	/* E4  : SATA_DEVSLP0 ==> PG_PPVAR_GPU_FBVDDQ_X_OD */
 	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
 	/* E5  : SATA_DEVSLP1 ==> PG_GPU_ALLRAILS */
@@ -89,7 +89,7 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
 	/* E10 : THC0_SPI1_CS# ==> EN_PP0950_GPU_X */
 	PAD_CFG_GPO_LOCK(GPP_E10, 0, LOCK_CONFIG),
-	/* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD */
+	/* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD (before board rev 3) */
 	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
 	/* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */
 	PAD_CFG_GPI(GPP_E17, NONE, DEEP),

src/mainboard/google/brya/variants/agah/variant.c

@@ -3,6 +3,7 @@
 #include <acpi/acpi.h>
 #include <acpi/acpigen.h>
 #include <baseboard/variants.h>
+#include <boardid.h>
 #include <delay.h>
 #include <device/pci_ops.h>
 #include <gpio.h>
@@ -14,7 +15,7 @@
 #define NV33_PWR_EN		GPP_A21
 #define NV33_PG			GPP_A22
 #define NVVDD_PWR_EN		GPP_E0
-#define NVVDD_PG		GPP_E16
+#define NVVDD_PG		GPP_E3
 #define PEXVDD_PWR_EN		GPP_E10
 #define PEXVDD_PG		GPP_E17
 #define FBVDD_PWR_EN		GPP_A19
@@ -46,7 +47,7 @@ struct power_rail_sequence {
 };
 
 /* In GCOFF exit order (i.e., power-on order) */
-static const struct power_rail_sequence gpu_on_seq[] = {
+static struct power_rail_sequence gpu_on_seq[] = {
 	{ "GPU 1.8V",		GPU_1V8_PWR_EN,	false, GPU_1V8_PG, },
 	{ "NV3_3",		NV33_PWR_EN,	false, NV33_PG, },
 	{ "NVVDD+MSVDD",	NVVDD_PWR_EN,	false, NVVDD_PG, },
@@ -55,7 +56,7 @@ static const struct power_rail_sequence gpu_on_seq[] = {
 };
 
 /* In GCOFF entry order (i.e., power-off order) */
-static const struct power_rail_sequence gpu_off_seq[] = {
+static struct power_rail_sequence gpu_off_seq[] = {
 	{ "FBVDD",		FBVDD_PWR_EN,	true,  FBVDD_PG,	0,},
 	{ "PEXVDD",		PEXVDD_PWR_EN,	false, PEXVDD_PG,	10,},
 	{ "NVVDD+MSVDD",	NVVDD_PWR_EN,	false, NVVDD_PG,	2,},
@@ -134,5 +135,29 @@ void variant_init(void)
 	if (acpi_is_wakeup_s3())
 		return;
 
+	/* For board revs 3 and later, the power good pin for the NVVDD
+	   VR moved from GPP_E16 to GPP_E3, so patch up the table for
+	   old board revs. */
+	if (board_id() < 3) {
+		gpu_on_seq[2].pg_gpio = GPP_E16;
+		gpu_off_seq[2].pg_gpio = GPP_E16;
+	}
+
 	dgpu_power_sequence_on();
 }
+
+/*
+ * For board revs 3 and later, the PG pin for the NVVDD VR moved from GPP_E16 to
+ * GPP_E3. To accommodate this, the DSDT contains a Name that this code will
+ * write the correct GPIO # to depending on the board rev, and we'll use that
+ * instead.
+ */
+void variant_fill_ssdt(const struct device *dev)
+{
+	const int nvvdd_pg_gpio = board_id() < 3 ? GPP_E16 : GPP_E3;
+	acpigen_write_scope("\\_SB.PCI0.PEG0.PEGP");
+	acpigen_write_method("_INI", 0);
+	acpigen_write_store_int_to_namestr(nvvdd_pg_gpio, "NVPG");
+	acpigen_write_method_end();
+	acpigen_write_scope_end();
+}